1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/interrupt-controller/amlogic,meson-gpio-intc.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Amlogic Meson GPIO interrupt controller 8 9maintainers: 10 - Heiner Kallweit <hkallweit1@gmail.com> 11 12description: | 13 Meson SoCs contains an interrupt controller which is able to watch the SoC 14 pads and generate an interrupt on edge or level. The controller is essentially 15 a 256 pads to 8 or 12 GIC interrupt multiplexer, with a filter block to select 16 edge or level and polarity. It does not expose all 256 mux inputs because the 17 documentation shows that the upper part is not mapped to any pad. The actual 18 number of interrupts exposed depends on the SoC. 19 20allOf: 21 - $ref: /schemas/interrupt-controller.yaml# 22 23properties: 24 compatible: 25 oneOf: 26 - const: amlogic,meson-gpio-intc 27 - items: 28 - enum: 29 - amlogic,meson8-gpio-intc 30 - amlogic,meson8b-gpio-intc 31 - amlogic,meson-gxbb-gpio-intc 32 - amlogic,meson-gxl-gpio-intc 33 - amlogic,meson-axg-gpio-intc 34 - amlogic,meson-g12a-gpio-intc 35 - amlogic,meson-sm1-gpio-intc 36 - amlogic,meson-a1-gpio-intc 37 - amlogic,meson-s4-gpio-intc 38 - const: amlogic,meson-gpio-intc 39 40 reg: 41 maxItems: 1 42 43 interrupt-controller: true 44 45 "#interrupt-cells": 46 const: 2 47 48 amlogic,channel-interrupts: 49 description: Array with the upstream hwirq numbers 50 minItems: 8 51 maxItems: 12 52 $ref: /schemas/types.yaml#/definitions/uint32-array 53 54required: 55 - compatible 56 - reg 57 - interrupt-controller 58 - "#interrupt-cells" 59 - amlogic,channel-interrupts 60 61additionalProperties: false 62 63examples: 64 - | 65 interrupt-controller@9880 { 66 compatible = "amlogic,meson-gxbb-gpio-intc", 67 "amlogic,meson-gpio-intc"; 68 reg = <0x9880 0x10>; 69 interrupt-controller; 70 #interrupt-cells = <2>; 71 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 72 }; 73