1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
8
9maintainers:
10  - Sibi Sankar <quic_sibis@quicinc.com>
11
12description:
13  L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
14  The OSM L3 interconnect provider aggregates the L3 bandwidth requests
15  from CPU/GPU and relays it to the OSM.
16
17properties:
18  compatible:
19    oneOf:
20      - items:
21          - enum:
22              - qcom,sc7180-osm-l3
23              - qcom,sc8180x-osm-l3
24              - qcom,sdm845-osm-l3
25              - qcom,sm8150-osm-l3
26          - const: qcom,osm-l3
27      - items:
28          - enum:
29              - qcom,sc7280-epss-l3
30              - qcom,sc8280xp-epss-l3
31              - qcom,sm8250-epss-l3
32              - qcom,sm8350-epss-l3
33          - const: qcom,epss-l3
34
35  reg:
36    maxItems: 1
37
38  clocks:
39    items:
40      - description: xo clock
41      - description: alternate clock
42
43  clock-names:
44    items:
45      - const: xo
46      - const: alternate
47
48  '#interconnect-cells':
49    const: 1
50
51required:
52  - compatible
53  - reg
54  - clocks
55  - clock-names
56  - '#interconnect-cells'
57
58additionalProperties: false
59
60examples:
61  - |
62
63    #define GPLL0               165
64    #define RPMH_CXO_CLK        0
65
66    osm_l3: interconnect@17d41000 {
67      compatible = "qcom,sdm845-osm-l3", "qcom,osm-l3";
68      reg = <0x17d41000 0x1400>;
69
70      clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
71      clock-names = "xo", "alternate";
72
73      #interconnect-cells = <1>;
74    };
75