1*061dbde2SShawn Guo# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*061dbde2SShawn Guo%YAML 1.2 3*061dbde2SShawn Guo--- 4*061dbde2SShawn Guo$id: http://devicetree.org/schemas/interconnect/qcom,qcm2290.yaml# 5*061dbde2SShawn Guo$schema: http://devicetree.org/meta-schemas/core.yaml# 6*061dbde2SShawn Guo 7*061dbde2SShawn Guotitle: Qualcomm QCM2290 Network-On-Chip interconnect 8*061dbde2SShawn Guo 9*061dbde2SShawn Guomaintainers: 10*061dbde2SShawn Guo - Shawn Guo <shawn.guo@linaro.org> 11*061dbde2SShawn Guo 12*061dbde2SShawn Guodescription: | 13*061dbde2SShawn Guo The Qualcomm QCM2290 interconnect providers support adjusting the 14*061dbde2SShawn Guo bandwidth requirements between the various NoC fabrics. 15*061dbde2SShawn Guo 16*061dbde2SShawn Guoproperties: 17*061dbde2SShawn Guo reg: 18*061dbde2SShawn Guo maxItems: 1 19*061dbde2SShawn Guo 20*061dbde2SShawn Guo compatible: 21*061dbde2SShawn Guo enum: 22*061dbde2SShawn Guo - qcom,qcm2290-bimc 23*061dbde2SShawn Guo - qcom,qcm2290-cnoc 24*061dbde2SShawn Guo - qcom,qcm2290-snoc 25*061dbde2SShawn Guo 26*061dbde2SShawn Guo '#interconnect-cells': 27*061dbde2SShawn Guo const: 1 28*061dbde2SShawn Guo 29*061dbde2SShawn Guo clock-names: 30*061dbde2SShawn Guo items: 31*061dbde2SShawn Guo - const: bus 32*061dbde2SShawn Guo - const: bus_a 33*061dbde2SShawn Guo 34*061dbde2SShawn Guo clocks: 35*061dbde2SShawn Guo items: 36*061dbde2SShawn Guo - description: Bus Clock 37*061dbde2SShawn Guo - description: Bus A Clock 38*061dbde2SShawn Guo 39*061dbde2SShawn Guo# Child node's properties 40*061dbde2SShawn GuopatternProperties: 41*061dbde2SShawn Guo '^interconnect-[a-z0-9]+$': 42*061dbde2SShawn Guo type: object 43*061dbde2SShawn Guo description: 44*061dbde2SShawn Guo The interconnect providers do not have a separate QoS register space, 45*061dbde2SShawn Guo but share parent's space. 46*061dbde2SShawn Guo 47*061dbde2SShawn Guo properties: 48*061dbde2SShawn Guo compatible: 49*061dbde2SShawn Guo enum: 50*061dbde2SShawn Guo - qcom,qcm2290-qup-virt 51*061dbde2SShawn Guo - qcom,qcm2290-mmrt-virt 52*061dbde2SShawn Guo - qcom,qcm2290-mmnrt-virt 53*061dbde2SShawn Guo 54*061dbde2SShawn Guo '#interconnect-cells': 55*061dbde2SShawn Guo const: 1 56*061dbde2SShawn Guo 57*061dbde2SShawn Guo clock-names: 58*061dbde2SShawn Guo items: 59*061dbde2SShawn Guo - const: bus 60*061dbde2SShawn Guo - const: bus_a 61*061dbde2SShawn Guo 62*061dbde2SShawn Guo clocks: 63*061dbde2SShawn Guo items: 64*061dbde2SShawn Guo - description: Bus Clock 65*061dbde2SShawn Guo - description: Bus A Clock 66*061dbde2SShawn Guo 67*061dbde2SShawn Guo required: 68*061dbde2SShawn Guo - compatible 69*061dbde2SShawn Guo - '#interconnect-cells' 70*061dbde2SShawn Guo - clock-names 71*061dbde2SShawn Guo - clocks 72*061dbde2SShawn Guo 73*061dbde2SShawn Guo additionalProperties: false 74*061dbde2SShawn Guo 75*061dbde2SShawn Guorequired: 76*061dbde2SShawn Guo - compatible 77*061dbde2SShawn Guo - reg 78*061dbde2SShawn Guo - '#interconnect-cells' 79*061dbde2SShawn Guo - clock-names 80*061dbde2SShawn Guo - clocks 81*061dbde2SShawn Guo 82*061dbde2SShawn GuoadditionalProperties: false 83*061dbde2SShawn Guo 84*061dbde2SShawn Guoexamples: 85*061dbde2SShawn Guo - | 86*061dbde2SShawn Guo #include <dt-bindings/clock/qcom,rpmcc.h> 87*061dbde2SShawn Guo 88*061dbde2SShawn Guo snoc: interconnect@1880000 { 89*061dbde2SShawn Guo compatible = "qcom,qcm2290-snoc"; 90*061dbde2SShawn Guo reg = <0x01880000 0x60200>; 91*061dbde2SShawn Guo #interconnect-cells = <1>; 92*061dbde2SShawn Guo clock-names = "bus", "bus_a"; 93*061dbde2SShawn Guo clocks = <&rpmcc RPM_SMD_SNOC_CLK>, 94*061dbde2SShawn Guo <&rpmcc RPM_SMD_SNOC_A_CLK>; 95*061dbde2SShawn Guo 96*061dbde2SShawn Guo qup_virt: interconnect-qup { 97*061dbde2SShawn Guo compatible = "qcom,qcm2290-qup-virt"; 98*061dbde2SShawn Guo #interconnect-cells = <1>; 99*061dbde2SShawn Guo clock-names = "bus", "bus_a"; 100*061dbde2SShawn Guo clocks = <&rpmcc RPM_SMD_QUP_CLK>, 101*061dbde2SShawn Guo <&rpmcc RPM_SMD_QUP_A_CLK>; 102*061dbde2SShawn Guo }; 103*061dbde2SShawn Guo 104*061dbde2SShawn Guo mmnrt_virt: interconnect-mmnrt { 105*061dbde2SShawn Guo compatible = "qcom,qcm2290-mmnrt-virt"; 106*061dbde2SShawn Guo #interconnect-cells = <1>; 107*061dbde2SShawn Guo clock-names = "bus", "bus_a"; 108*061dbde2SShawn Guo clocks = <&rpmcc RPM_SMD_MMNRT_CLK>, 109*061dbde2SShawn Guo <&rpmcc RPM_SMD_MMNRT_A_CLK>; 110*061dbde2SShawn Guo }; 111*061dbde2SShawn Guo 112*061dbde2SShawn Guo mmrt_virt: interconnect-mmrt { 113*061dbde2SShawn Guo compatible = "qcom,qcm2290-mmrt-virt"; 114*061dbde2SShawn Guo #interconnect-cells = <1>; 115*061dbde2SShawn Guo clock-names = "bus", "bus_a"; 116*061dbde2SShawn Guo clocks = <&rpmcc RPM_SMD_MMRT_CLK>, 117*061dbde2SShawn Guo <&rpmcc RPM_SMD_MMRT_A_CLK>; 118*061dbde2SShawn Guo }; 119*061dbde2SShawn Guo }; 120*061dbde2SShawn Guo 121*061dbde2SShawn Guo cnoc: interconnect@1900000 { 122*061dbde2SShawn Guo compatible = "qcom,qcm2290-cnoc"; 123*061dbde2SShawn Guo reg = <0x01900000 0x8200>; 124*061dbde2SShawn Guo #interconnect-cells = <1>; 125*061dbde2SShawn Guo clock-names = "bus", "bus_a"; 126*061dbde2SShawn Guo clocks = <&rpmcc RPM_SMD_CNOC_CLK>, 127*061dbde2SShawn Guo <&rpmcc RPM_SMD_CNOC_A_CLK>; 128*061dbde2SShawn Guo }; 129*061dbde2SShawn Guo 130*061dbde2SShawn Guo bimc: interconnect@4480000 { 131*061dbde2SShawn Guo compatible = "qcom,qcm2290-bimc"; 132*061dbde2SShawn Guo reg = <0x04480000 0x80000>; 133*061dbde2SShawn Guo #interconnect-cells = <1>; 134*061dbde2SShawn Guo clock-names = "bus", "bus_a"; 135*061dbde2SShawn Guo clocks = <&rpmcc RPM_SMD_BIMC_CLK>, 136*061dbde2SShawn Guo <&rpmcc RPM_SMD_BIMC_A_CLK>; 137*061dbde2SShawn Guo }; 138