1146eee03SLeonard Crestez# SPDX-License-Identifier: GPL-2.0 2146eee03SLeonard Crestez%YAML 1.2 3146eee03SLeonard Crestez--- 4146eee03SLeonard Crestez$id: http://devicetree.org/schemas/interconnect/fsl,imx8m-noc.yaml# 5146eee03SLeonard Crestez$schema: http://devicetree.org/meta-schemas/core.yaml# 6146eee03SLeonard Crestez 7146eee03SLeonard Cresteztitle: Generic i.MX bus frequency device 8146eee03SLeonard Crestez 9146eee03SLeonard Crestezmaintainers: 10146eee03SLeonard Crestez - Leonard Crestez <leonard.crestez@nxp.com> 11146eee03SLeonard Crestez 12146eee03SLeonard Crestezdescription: | 13146eee03SLeonard Crestez The i.MX SoC family has multiple buses for which clock frequency (and 14146eee03SLeonard Crestez sometimes voltage) can be adjusted. 15146eee03SLeonard Crestez 16146eee03SLeonard Crestez Some of those buses expose register areas mentioned in the memory maps as GPV 17146eee03SLeonard Crestez ("Global Programmers View") but not all. Access to this area might be denied 18146eee03SLeonard Crestez for normal (non-secure) world. 19146eee03SLeonard Crestez 20146eee03SLeonard Crestez The buses are based on externally licensed IPs such as ARM NIC-301 and 21146eee03SLeonard Crestez Arteris FlexNOC but DT bindings are specific to the integration of these bus 22146eee03SLeonard Crestez interconnect IPs into imx SOCs. 23146eee03SLeonard Crestez 24146eee03SLeonard Crestezproperties: 25146eee03SLeonard Crestez compatible: 26146eee03SLeonard Crestez oneOf: 27146eee03SLeonard Crestez - items: 28146eee03SLeonard Crestez - enum: 29146eee03SLeonard Crestez - fsl,imx8mn-nic 30146eee03SLeonard Crestez - fsl,imx8mm-nic 31146eee03SLeonard Crestez - fsl,imx8mq-nic 32146eee03SLeonard Crestez - const: fsl,imx8m-nic 33146eee03SLeonard Crestez - items: 34146eee03SLeonard Crestez - enum: 35146eee03SLeonard Crestez - fsl,imx8mn-noc 36146eee03SLeonard Crestez - fsl,imx8mm-noc 37146eee03SLeonard Crestez - fsl,imx8mq-noc 38146eee03SLeonard Crestez - const: fsl,imx8m-noc 39146eee03SLeonard Crestez - const: fsl,imx8m-nic 40146eee03SLeonard Crestez 41146eee03SLeonard Crestez reg: 42146eee03SLeonard Crestez maxItems: 1 43146eee03SLeonard Crestez 44146eee03SLeonard Crestez clocks: 45146eee03SLeonard Crestez maxItems: 1 46146eee03SLeonard Crestez 47146eee03SLeonard Crestez operating-points-v2: true 48146eee03SLeonard Crestez opp-table: true 49146eee03SLeonard Crestez 50146eee03SLeonard Crestez fsl,ddrc: 51146eee03SLeonard Crestez $ref: "/schemas/types.yaml#/definitions/phandle" 52146eee03SLeonard Crestez description: 53146eee03SLeonard Crestez Phandle to DDR Controller. 54146eee03SLeonard Crestez 55146eee03SLeonard Crestez '#interconnect-cells': 56146eee03SLeonard Crestez description: 57146eee03SLeonard Crestez If specified then also act as an interconnect provider. Should only be 58146eee03SLeonard Crestez set once per soc on the main noc. 59146eee03SLeonard Crestez const: 1 60146eee03SLeonard Crestez 61146eee03SLeonard Crestezrequired: 62146eee03SLeonard Crestez - compatible 63146eee03SLeonard Crestez - clocks 64146eee03SLeonard Crestez 65146eee03SLeonard CrestezadditionalProperties: false 66146eee03SLeonard Crestez 67146eee03SLeonard Crestezexamples: 68146eee03SLeonard Crestez - | 69146eee03SLeonard Crestez #include <dt-bindings/clock/imx8mm-clock.h> 70146eee03SLeonard Crestez #include <dt-bindings/interconnect/imx8mm.h> 71146eee03SLeonard Crestez #include <dt-bindings/interrupt-controller/arm-gic.h> 72146eee03SLeonard Crestez 73146eee03SLeonard Crestez noc: interconnect@32700000 { 74146eee03SLeonard Crestez compatible = "fsl,imx8mm-noc", "fsl,imx8m-noc"; 75146eee03SLeonard Crestez reg = <0x32700000 0x100000>; 76146eee03SLeonard Crestez clocks = <&clk IMX8MM_CLK_NOC>; 77146eee03SLeonard Crestez #interconnect-cells = <1>; 78146eee03SLeonard Crestez fsl,ddrc = <&ddrc>; 79146eee03SLeonard Crestez 80146eee03SLeonard Crestez operating-points-v2 = <&noc_opp_table>; 81146eee03SLeonard Crestez noc_opp_table: opp-table { 82146eee03SLeonard Crestez compatible = "operating-points-v2"; 83146eee03SLeonard Crestez 84*29fc7695SRob Herring opp-133333333 { 85146eee03SLeonard Crestez opp-hz = /bits/ 64 <133333333>; 86146eee03SLeonard Crestez }; 87*29fc7695SRob Herring opp-800000000 { 88146eee03SLeonard Crestez opp-hz = /bits/ 64 <800000000>; 89146eee03SLeonard Crestez }; 90146eee03SLeonard Crestez }; 91146eee03SLeonard Crestez }; 92146eee03SLeonard Crestez 93146eee03SLeonard Crestez ddrc: memory-controller@3d400000 { 94146eee03SLeonard Crestez compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc"; 95146eee03SLeonard Crestez reg = <0x3d400000 0x400000>; 96146eee03SLeonard Crestez clock-names = "core", "pll", "alt", "apb"; 97146eee03SLeonard Crestez clocks = <&clk IMX8MM_CLK_DRAM_CORE>, 98146eee03SLeonard Crestez <&clk IMX8MM_DRAM_PLL>, 99146eee03SLeonard Crestez <&clk IMX8MM_CLK_DRAM_ALT>, 100146eee03SLeonard Crestez <&clk IMX8MM_CLK_DRAM_APB>; 101146eee03SLeonard Crestez }; 102