1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: "http://devicetree.org/schemas/iio/adc/st,stm32-adc.yaml#"
5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
6
7title: STMicroelectronics STM32 ADC bindings
8
9description: |
10  STM32 ADC is a successive approximation analog-to-digital converter.
11  It has several multiplexed input channels. Conversions can be performed
12  in single, continuous, scan or discontinuous mode. Result of the ADC is
13  stored in a left-aligned or right-aligned 32-bit data register.
14  Conversions can be launched in software or using hardware triggers.
15
16  The analog watchdog feature allows the application to detect if the input
17  voltage goes beyond the user-defined, higher or lower thresholds.
18
19  Each STM32 ADC block can have up to 3 ADC instances.
20
21maintainers:
22  - Fabrice Gasnier <fabrice.gasnier@st.com>
23
24properties:
25  compatible:
26    enum:
27      - st,stm32f4-adc-core
28      - st,stm32h7-adc-core
29      - st,stm32mp1-adc-core
30
31  reg:
32    maxItems: 1
33
34  interrupts:
35    description: |
36      One or more interrupts for ADC block, depending on part used:
37        - stm32f4 and stm32h7 share a common ADC interrupt line.
38        - stm32mp1 has two separate interrupt lines, one for each ADC within
39          ADC block.
40    minItems: 1
41    maxItems: 2
42
43  clocks:
44    minItems: 1
45    maxItems: 2
46    description: |
47      Core can use up to two clocks, depending on part used:
48        - "adc" clock: for the analog circuitry, common to all ADCs.
49          It's required on stm32f4.
50          It's optional on stm32h7 and stm32mp1.
51        - "bus" clock: for registers access, common to all ADCs.
52          It's not present on stm32f4.
53          It's required on stm32h7 and stm32mp1.
54
55  clock-names: true
56
57  st,max-clk-rate-hz:
58    description:
59      Allow to specify desired max clock rate used by analog circuitry.
60
61  vdda-supply:
62    description: Phandle to the vdda input analog voltage.
63
64  vref-supply:
65    description: Phandle to the vref input analog reference voltage.
66
67  booster-supply:
68    description:
69      Phandle to the embedded booster regulator that can be used to supply ADC
70      analog input switches on stm32h7 and stm32mp1.
71
72  vdd-supply:
73    description:
74      Phandle to the vdd input voltage. It can be used to supply ADC analog
75      input switches on stm32mp1.
76
77  st,syscfg:
78    description:
79      Phandle to system configuration controller. It can be used to control the
80      analog circuitry on stm32mp1.
81    $ref: "/schemas/types.yaml#/definitions/phandle-array"
82
83  interrupt-controller: true
84
85  '#interrupt-cells':
86    const: 1
87
88  '#address-cells':
89    const: 1
90
91  '#size-cells':
92    const: 0
93
94allOf:
95  - if:
96      properties:
97        compatible:
98          contains:
99            const: st,stm32f4-adc-core
100
101    then:
102      properties:
103        clocks:
104          maxItems: 1
105
106        clock-names:
107          const: adc
108
109        interrupts:
110          items:
111            - description: interrupt line common for all ADCs
112
113        st,max-clk-rate-hz:
114          minimum: 600000
115          maximum: 36000000
116          default: 36000000
117
118        booster-supply: false
119
120        vdd-supply: false
121
122        st,syscfg: false
123
124  - if:
125      properties:
126        compatible:
127          contains:
128            const: st,stm32h7-adc-core
129
130    then:
131      properties:
132        clocks:
133          minItems: 1
134          maxItems: 2
135
136        clock-names:
137          items:
138            - const: bus
139            - const: adc
140          minItems: 1
141          maxItems: 2
142
143        interrupts:
144          items:
145            - description: interrupt line common for all ADCs
146
147        st,max-clk-rate-hz:
148          minimum: 120000
149          maximum: 36000000
150          default: 36000000
151
152        vdd-supply: false
153
154        st,syscfg: false
155
156  - if:
157      properties:
158        compatible:
159          contains:
160            const: st,stm32mp1-adc-core
161
162    then:
163      properties:
164        clocks:
165          minItems: 1
166          maxItems: 2
167
168        clock-names:
169          items:
170            - const: bus
171            - const: adc
172          minItems: 1
173          maxItems: 2
174
175        interrupts:
176          items:
177            - description: interrupt line for ADC1
178            - description: interrupt line for ADC2
179
180        st,max-clk-rate-hz:
181          minimum: 120000
182          maximum: 36000000
183          default: 36000000
184
185additionalProperties: false
186
187required:
188  - compatible
189  - reg
190  - interrupts
191  - clocks
192  - clock-names
193  - vdda-supply
194  - vref-supply
195  - interrupt-controller
196  - '#interrupt-cells'
197  - '#address-cells'
198  - '#size-cells'
199
200patternProperties:
201  "^adc@[0-9]+$":
202    type: object
203    description:
204      An ADC block node should contain at least one subnode, representing an
205      ADC instance available on the machine.
206
207    properties:
208      compatible:
209        enum:
210          - st,stm32f4-adc
211          - st,stm32h7-adc
212          - st,stm32mp1-adc
213
214      reg:
215        description: |
216          Offset of ADC instance in ADC block. Valid values are:
217            - 0x0:   ADC1
218            - 0x100: ADC2
219            - 0x200: ADC3 (stm32f4 only)
220        maxItems: 1
221
222      '#io-channel-cells':
223        const: 1
224
225      interrupts:
226        description: |
227          IRQ Line for the ADC instance. Valid values are:
228            - 0 for adc@0
229            - 1 for adc@100
230            - 2 for adc@200 (stm32f4 only)
231        maxItems: 1
232
233      clocks:
234        description:
235          Input clock private to this ADC instance. It's required only on
236          stm32f4, that has per instance clock input for registers access.
237        maxItems: 1
238
239      dmas:
240        description: RX DMA Channel
241        maxItems: 1
242
243      dma-names:
244        const: rx
245
246      assigned-resolution-bits:
247        description: |
248          Resolution (bits) to use for conversions:
249            - can be 6, 8, 10 or 12 on stm32f4
250            - can be 8, 10, 12, 14 or 16 on stm32h7 and stm32mp1
251        $ref: /schemas/types.yaml#/definitions/uint32
252
253      st,adc-channels:
254        description: |
255          List of single-ended channels muxed for this ADC. It can have up to:
256            - 16 channels, numbered from 0 to 15 (for in0..in15) on stm32f4
257            - 20 channels, numbered from 0 to 19 (for in0..in19) on stm32h7 and
258              stm32mp1.
259        $ref: /schemas/types.yaml#/definitions/uint32-array
260
261      st,adc-diff-channels:
262        description: |
263          List of differential channels muxed for this ADC. Some channels can
264          be configured as differential instead of single-ended on stm32h7 and
265          on stm32mp1. Positive and negative inputs pairs are listed:
266          <vinp vinn>, <vinp vinn>,... vinp and vinn are numbered from 0 to 19.
267
268          Note: At least one of "st,adc-channels" or "st,adc-diff-channels" is
269          required. Both properties can be used together. Some channels can be
270          used as single-ended and some other ones as differential (mixed). But
271          channels can't be configured both as single-ended and differential.
272        $ref: /schemas/types.yaml#/definitions/uint32-matrix
273        items:
274          items:
275            - description: |
276                "vinp" indicates positive input number
277              minimum: 0
278              maximum: 19
279            - description: |
280                "vinn" indicates negative input number
281              minimum: 0
282              maximum: 19
283
284      st,min-sample-time-nsecs:
285        description:
286          Minimum sampling time in nanoseconds. Depending on hardware (board)
287          e.g. high/low analog input source impedance, fine tune of ADC
288          sampling time may be recommended. This can be either one value or an
289          array that matches "st,adc-channels" and/or "st,adc-diff-channels"
290          list, to set sample time resp. for all channels, or independently for
291          each channel.
292        $ref: /schemas/types.yaml#/definitions/uint32-array
293
294    allOf:
295      - if:
296          properties:
297            compatible:
298              contains:
299                const: st,stm32f4-adc
300
301        then:
302          properties:
303            reg:
304              enum:
305                - 0x0
306                - 0x100
307                - 0x200
308
309            interrupts:
310              minimum: 0
311              maximum: 2
312
313            assigned-resolution-bits:
314              enum: [6, 8, 10, 12]
315              default: 12
316
317            st,adc-channels:
318              minItems: 1
319              maxItems: 16
320              items:
321                minimum: 0
322                maximum: 15
323
324            st,adc-diff-channels: false
325
326            st,min-sample-time-nsecs:
327              minItems: 1
328              maxItems: 16
329              items:
330                minimum: 80
331
332          required:
333            - clocks
334
335      - if:
336          properties:
337            compatible:
338              contains:
339                enum:
340                  - st,stm32h7-adc
341                  - st,stm32mp1-adc
342
343        then:
344          properties:
345            reg:
346              enum:
347                - 0x0
348                - 0x100
349
350            interrupts:
351              minimum: 0
352              maximum: 1
353
354            assigned-resolution-bits:
355              enum: [8, 10, 12, 14, 16]
356              default: 16
357
358            st,adc-channels:
359              minItems: 1
360              maxItems: 20
361              items:
362                minimum: 0
363                maximum: 19
364
365            st,min-sample-time-nsecs:
366              minItems: 1
367              maxItems: 20
368              items:
369                minimum: 40
370
371    additionalProperties: false
372
373    anyOf:
374      - required:
375          - st,adc-channels
376      - required:
377          - st,adc-diff-channels
378
379    required:
380      - compatible
381      - reg
382      - interrupts
383      - '#io-channel-cells'
384
385examples:
386  - |
387    // Example 1: with stm32f429, ADC1, single-ended channel 8
388      adc123: adc@40012000 {
389        compatible = "st,stm32f4-adc-core";
390        reg = <0x40012000 0x400>;
391        interrupts = <18>;
392        clocks = <&rcc 0 168>;
393        clock-names = "adc";
394        st,max-clk-rate-hz = <36000000>;
395        vdda-supply = <&vdda>;
396        vref-supply = <&vref>;
397        interrupt-controller;
398        #interrupt-cells = <1>;
399        #address-cells = <1>;
400        #size-cells = <0>;
401        adc@0 {
402          compatible = "st,stm32f4-adc";
403          #io-channel-cells = <1>;
404          reg = <0x0>;
405          clocks = <&rcc 0 168>;
406          interrupt-parent = <&adc123>;
407          interrupts = <0>;
408          st,adc-channels = <8>;
409          dmas = <&dma2 0 0 0x400 0x0>;
410          dma-names = "rx";
411          assigned-resolution-bits = <8>;
412        };
413        // ...
414        // other adc child nodes follow...
415      };
416
417  - |
418    // Example 2: with stm32mp157c to setup ADC1 with:
419    // - channels 0 & 1 as single-ended
420    // - channels 2 & 3 as differential (with resp. 6 & 7 negative inputs)
421      #include <dt-bindings/interrupt-controller/arm-gic.h>
422      #include <dt-bindings/clock/stm32mp1-clks.h>
423      adc12: adc@48003000 {
424        compatible = "st,stm32mp1-adc-core";
425        reg = <0x48003000 0x400>;
426        interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
427                     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
428        clocks = <&rcc ADC12>, <&rcc ADC12_K>;
429        clock-names = "bus", "adc";
430        booster-supply = <&booster>;
431        vdd-supply = <&vdd>;
432        vdda-supply = <&vdda>;
433        vref-supply = <&vref>;
434        st,syscfg = <&syscfg>;
435        interrupt-controller;
436        #interrupt-cells = <1>;
437        #address-cells = <1>;
438        #size-cells = <0>;
439        adc@0 {
440          compatible = "st,stm32mp1-adc";
441          #io-channel-cells = <1>;
442          reg = <0x0>;
443          interrupt-parent = <&adc12>;
444          interrupts = <0>;
445          st,adc-channels = <0 1>;
446          st,adc-diff-channels = <2 6>, <3 7>;
447          st,min-sample-time-nsecs = <5000>;
448          dmas = <&dmamux1 9 0x400 0x05>;
449          dma-names = "rx";
450        };
451        // ...
452        // other adc child node follow...
453      };
454
455...
456