1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP IMX8QXP ADC
8
9maintainers:
10  - Cai Huoqing <caihuoqing@baidu.com>
11
12description:
13  Supports the ADC found on the IMX8QXP SoC.
14
15properties:
16  compatible:
17    const: nxp,imx8qxp-adc
18
19  reg:
20    maxItems: 1
21
22  interrupts:
23    maxItems: 1
24
25  clocks:
26    maxItems: 2
27
28  clock-names:
29    items:
30      - const: per
31      - const: ipg
32
33  assigned-clocks:
34    maxItems: 1
35
36  assigned-clock-rates:
37    maxItems: 1
38
39  power-domains:
40    maxItems: 1
41
42  vref-supply:
43    description: |
44      External ADC reference voltage supply on VREFH pad. If VERID[MVI] is
45      set, there are additional, internal reference voltages selectable.
46      VREFH1 is always from VREFH pad.
47
48  "#io-channel-cells":
49    const: 1
50
51required:
52  - compatible
53  - reg
54  - interrupts
55  - clocks
56  - clock-names
57  - assigned-clocks
58  - assigned-clock-rates
59  - power-domains
60  - "#io-channel-cells"
61
62additionalProperties: false
63
64examples:
65  - |
66    #include <dt-bindings/interrupt-controller/arm-gic.h>
67    #include <dt-bindings/firmware/imx/rsrc.h>
68    soc {
69        #address-cells = <2>;
70        #size-cells = <2>;
71        adc@5a880000 {
72            compatible = "nxp,imx8qxp-adc";
73            reg = <0x0 0x5a880000 0x0 0x10000>;
74            interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
75            clocks = <&clk IMX_SC_R_ADC_0>,
76                     <&clk IMX_SC_R_ADC_0>;
77            clock-names = "per", "ipg";
78            assigned-clocks = <&clk IMX_SC_R_ADC_0>;
79            assigned-clock-rates = <24000000>;
80            power-domains = <&pd IMX_SC_R_ADC_0>;
81            vref-supply = <&reg_1v8>;
82            #io-channel-cells = <1>;
83        };
84    };
85...
86