1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: I2C controller embedded in STMicroelectronics STM32 I2C platform
8
9maintainers:
10  - Pierre-Yves MORDRET <pierre-yves.mordret@st.com>
11
12allOf:
13  - $ref: /schemas/i2c/i2c-controller.yaml#
14  - if:
15      properties:
16        compatible:
17          contains:
18            enum:
19              - st,stm32f7-i2c
20              - st,stm32mp15-i2c
21    then:
22      properties:
23        i2c-scl-rising-time-ns:
24          default: 25
25
26        i2c-scl-falling-time-ns:
27          default: 10
28
29        st,syscfg-fmp:
30          description: Use to set Fast Mode Plus bit within SYSCFG when
31                       Fast Mode Plus speed is selected by slave.
32                       Format is phandle to syscfg / register offset within
33                       syscfg / register bitmask for FMP bit.
34          $ref: "/schemas/types.yaml#/definitions/phandle-array"
35          items:
36            minItems: 3
37            maxItems: 3
38
39  - if:
40      properties:
41        compatible:
42          contains:
43            enum:
44              - st,stm32f4-i2c
45    then:
46      properties:
47        clock-frequency:
48          enum: [100000, 400000]
49
50properties:
51  compatible:
52    enum:
53      - st,stm32f4-i2c
54      - st,stm32f7-i2c
55      - st,stm32mp15-i2c
56
57  reg:
58    maxItems: 1
59
60  interrupts:
61    items:
62      - description: interrupt ID for I2C event
63      - description: interrupt ID for I2C error
64
65  resets:
66    maxItems: 1
67
68  clocks:
69    maxItems: 1
70
71  dmas:
72    items:
73      - description: RX DMA Channel phandle
74      - description: TX DMA Channel phandle
75
76  dma-names:
77    items:
78      - const: rx
79      - const: tx
80
81  clock-frequency:
82    description: Desired I2C bus clock frequency in Hz. If not specified,
83                 the default 100 kHz frequency will be used.
84                 For STM32F7, STM32H7 and STM32MP1 SoCs, Standard-mode,
85                 Fast-mode and Fast-mode Plus are supported, possible
86                 values are 100000, 400000 and 1000000.
87    default: 100000
88    enum: [100000, 400000, 1000000]
89
90required:
91  - compatible
92  - reg
93  - interrupts
94  - resets
95  - clocks
96
97examples:
98  - |
99    #include <dt-bindings/mfd/stm32f7-rcc.h>
100    #include <dt-bindings/clock/stm32fx-clock.h>
101    //Example 1 (with st,stm32f4-i2c compatible)
102      i2c@40005400 {
103          compatible = "st,stm32f4-i2c";
104          #address-cells = <1>;
105          #size-cells = <0>;
106          reg = <0x40005400 0x400>;
107          interrupts = <31>,
108                       <32>;
109          resets = <&rcc 277>;
110          clocks = <&rcc 0 149>;
111      };
112
113    //Example 2 (with st,stm32f7-i2c compatible)
114      i2c@40005800 {
115          compatible = "st,stm32f7-i2c";
116          #address-cells = <1>;
117          #size-cells = <0>;
118          reg = <0x40005800 0x400>;
119          interrupts = <31>,
120                       <32>;
121          resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
122          clocks = <&rcc 1 CLK_I2C1>;
123      };
124
125    //Example 3 (with st,stm32mp15-i2c compatible on stm32mp)
126    #include <dt-bindings/interrupt-controller/arm-gic.h>
127    #include <dt-bindings/clock/stm32mp1-clks.h>
128    #include <dt-bindings/reset/stm32mp1-resets.h>
129      i2c@40013000 {
130          compatible = "st,stm32mp15-i2c";
131          #address-cells = <1>;
132          #size-cells = <0>;
133          reg = <0x40013000 0x400>;
134          interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
135                       <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
136          clocks = <&rcc I2C2_K>;
137          resets = <&rcc I2C2_R>;
138          i2c-scl-rising-time-ns = <185>;
139          i2c-scl-falling-time-ns = <20>;
140          st,syscfg-fmp = <&syscfg 0x4 0x2>;
141      };
142...
143