1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/st,stm32-i2c.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: I2C controller embedded in STMicroelectronics STM32 I2C platform
8
9maintainers:
10  - Pierre-Yves MORDRET <pierre-yves.mordret@foss.st.com>
11
12allOf:
13  - $ref: /schemas/i2c/i2c-controller.yaml#
14  - if:
15      properties:
16        compatible:
17          contains:
18            enum:
19              - st,stm32f7-i2c
20              - st,stm32mp13-i2c
21              - st,stm32mp15-i2c
22    then:
23      properties:
24        i2c-scl-rising-time-ns:
25          default: 25
26
27        i2c-scl-falling-time-ns:
28          default: 10
29    else:
30      properties:
31        st,syscfg-fmp: false
32
33  - if:
34      properties:
35        compatible:
36          contains:
37            enum:
38              - st,stm32f4-i2c
39    then:
40      properties:
41        clock-frequency:
42          enum: [100000, 400000]
43
44properties:
45  compatible:
46    enum:
47      - st,stm32f4-i2c
48      - st,stm32f7-i2c
49      - st,stm32mp13-i2c
50      - st,stm32mp15-i2c
51
52  reg:
53    maxItems: 1
54
55  interrupts:
56    items:
57      - description: interrupt ID for I2C event
58      - description: interrupt ID for I2C error
59
60  resets:
61    maxItems: 1
62
63  clocks:
64    maxItems: 1
65
66  dmas:
67    items:
68      - description: RX DMA Channel phandle
69      - description: TX DMA Channel phandle
70
71  dma-names:
72    items:
73      - const: rx
74      - const: tx
75
76  clock-frequency:
77    description: Desired I2C bus clock frequency in Hz. If not specified,
78                 the default 100 kHz frequency will be used.
79                 For STM32F7, STM32H7 and STM32MP1 SoCs, if timing parameters
80                 match, the bus clock frequency can be from 1Hz to 1MHz.
81    default: 100000
82    minimum: 1
83    maximum: 1000000
84
85  st,syscfg-fmp:
86    description: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode
87      Plus speed is selected by slave.
88    $ref: "/schemas/types.yaml#/definitions/phandle-array"
89    items:
90      - items:
91          - description: phandle to syscfg
92          - description: register offset within syscfg
93          - description: register bitmask for FMP bit
94
95required:
96  - compatible
97  - reg
98  - interrupts
99  - resets
100  - clocks
101
102unevaluatedProperties: false
103
104examples:
105  - |
106    #include <dt-bindings/mfd/stm32f7-rcc.h>
107    #include <dt-bindings/clock/stm32fx-clock.h>
108    //Example 1 (with st,stm32f4-i2c compatible)
109      i2c@40005400 {
110          compatible = "st,stm32f4-i2c";
111          #address-cells = <1>;
112          #size-cells = <0>;
113          reg = <0x40005400 0x400>;
114          interrupts = <31>,
115                       <32>;
116          resets = <&rcc 277>;
117          clocks = <&rcc 0 149>;
118      };
119
120  - |
121    #include <dt-bindings/mfd/stm32f7-rcc.h>
122    #include <dt-bindings/clock/stm32fx-clock.h>
123    //Example 2 (with st,stm32f7-i2c compatible)
124      i2c@40005800 {
125          compatible = "st,stm32f7-i2c";
126          #address-cells = <1>;
127          #size-cells = <0>;
128          reg = <0x40005800 0x400>;
129          interrupts = <31>,
130                       <32>;
131          resets = <&rcc STM32F7_APB1_RESET(I2C1)>;
132          clocks = <&rcc 1 CLK_I2C1>;
133      };
134
135  - |
136    #include <dt-bindings/mfd/stm32f7-rcc.h>
137    #include <dt-bindings/clock/stm32fx-clock.h>
138    //Example 3 (with st,stm32mp15-i2c compatible on stm32mp)
139    #include <dt-bindings/interrupt-controller/arm-gic.h>
140    #include <dt-bindings/clock/stm32mp1-clks.h>
141    #include <dt-bindings/reset/stm32mp1-resets.h>
142      i2c@40013000 {
143          compatible = "st,stm32mp15-i2c";
144          #address-cells = <1>;
145          #size-cells = <0>;
146          reg = <0x40013000 0x400>;
147          interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
148                       <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
149          clocks = <&rcc I2C2_K>;
150          resets = <&rcc I2C2_R>;
151          i2c-scl-rising-time-ns = <185>;
152          i2c-scl-falling-time-ns = <20>;
153          st,syscfg-fmp = <&syscfg 0x4 0x2>;
154      };
155