1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare APB I2C Controller
8
9maintainers:
10  - Jarkko Nikula <jarkko.nikula@linux.intel.com>
11
12allOf:
13  - $ref: /schemas/i2c/i2c-controller.yaml#
14  - if:
15      properties:
16        compatible:
17          not:
18            contains:
19              const: mscc,ocelot-i2c
20    then:
21      properties:
22        reg:
23          maxItems: 1
24
25properties:
26  compatible:
27    oneOf:
28      - description: Generic Synopsys DesignWare I2C controller
29        const: snps,designware-i2c
30      - description: Microsemi Ocelot SoCs I2C controller
31        items:
32          - const: mscc,ocelot-i2c
33          - const: snps,designware-i2c
34
35  reg:
36    minItems: 1
37    items:
38      - description: DW APB I2C controller memory mapped registers
39      - description: |
40          ICPU_CFG:TWI_DELAY registers to setup the SDA hold time.
41          This registers are specific to the Ocelot I2C-controller.
42
43  interrupts:
44    maxItems: 1
45
46  clocks:
47    minItems: 1
48    items:
49      - description: I2C controller reference clock source
50      - description: APB interface clock source
51
52  clock-names:
53    minItems: 1
54    items:
55      - const: ref
56      - const: pclk
57
58  resets:
59    maxItems: 1
60
61  clock-frequency:
62    description: Desired I2C bus clock frequency in Hz
63    enum: [100000, 400000, 1000000, 3400000]
64    default: 400000
65
66  i2c-sda-hold-time-ns:
67    maxItems: 1
68    description: |
69      The property should contain the SDA hold time in nanoseconds. This option
70      is only supported in hardware blocks version 1.11a or newer or on
71      Microsemi SoCs.
72
73  i2c-scl-falling-time-ns:
74    maxItems: 1
75    description: |
76      The property should contain the SCL falling time in nanoseconds.
77      This value is used to compute the tLOW period.
78    default: 300
79
80  i2c-sda-falling-time-ns:
81    maxItems: 1
82    description: |
83      The property should contain the SDA falling time in nanoseconds.
84      This value is used to compute the tHIGH period.
85    default: 300
86
87  dmas:
88    items:
89      - description: TX DMA Channel
90      - description: RX DMA Channel
91
92  dma-names:
93    items:
94      - const: tx
95      - const: rx
96
97unevaluatedProperties: false
98
99required:
100  - compatible
101  - reg
102  - "#address-cells"
103  - "#size-cells"
104  - interrupts
105
106examples:
107  - |
108    i2c@f0000 {
109      compatible = "snps,designware-i2c";
110      reg = <0xf0000 0x1000>;
111      #address-cells = <1>;
112      #size-cells = <0>;
113      interrupts = <11>;
114      clock-frequency = <400000>;
115    };
116  - |
117    i2c@1120000 {
118      compatible = "snps,designware-i2c";
119      reg = <0x1120000 0x1000>;
120      #address-cells = <1>;
121      #size-cells = <0>;
122      interrupts = <12 1>;
123      clock-frequency = <400000>;
124      i2c-sda-hold-time-ns = <300>;
125      i2c-sda-falling-time-ns = <300>;
126      i2c-scl-falling-time-ns = <300>;
127    };
128  - |
129    i2c@2000 {
130      compatible = "snps,designware-i2c";
131      reg = <0x2000 0x100>;
132      #address-cells = <1>;
133      #size-cells = <0>;
134      clock-frequency = <400000>;
135      clocks = <&i2cclk>;
136      interrupts = <0>;
137
138      eeprom@64 {
139        compatible = "atmel,24c02";
140        reg = <0x64>;
141      };
142    };
143  - |
144    i2c@100400 {
145      compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
146      reg = <0x100400 0x100>, <0x198 0x8>;
147      pinctrl-0 = <&i2c_pins>;
148      pinctrl-names = "default";
149      #address-cells = <1>;
150      #size-cells = <0>;
151      interrupts = <8>;
152      clocks = <&ahb_clk>;
153    };
154...
155