1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/renesas,riic.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas RZ/A and RZ/G2L I2C Bus Interface (RIIC)
8
9maintainers:
10  - Chris Brandt <chris.brandt@renesas.com>
11  - Wolfram Sang <wsa+renesas@sang-engineering.com>
12
13allOf:
14  - $ref: /schemas/i2c/i2c-controller.yaml#
15
16properties:
17  compatible:
18    items:
19      - enum:
20          - renesas,riic-r7s72100   # RZ/A1H
21          - renesas,riic-r7s9210    # RZ/A2M
22          - renesas,riic-r9a07g044  # RZ/G2{L,LC}
23      - const: renesas,riic-rz      # RZ/A or RZ/G2L
24
25  reg:
26    maxItems: 1
27
28  interrupts:
29    items:
30      - description: Transmit End Interrupt (TEI)
31      - description: Receive Data Full Interrupt (RI)
32      - description: Transmit Data Empty Interrupt (TI)
33      - description: Stop Condition Detection Interrupt (SPI)
34      - description: Start Condition Detection Interrupt (STI)
35      - description: NACK Reception Interrupt (NAKI)
36      - description: Arbitration-Lost Interrupt (ALI)
37      - description: Timeout Interrupt (TMOI)
38
39  clock-frequency:
40    description:
41      Desired I2C bus clock frequency in Hz. The absence of this property
42      indicates the default frequency 100 kHz.
43
44  clocks:
45    maxItems: 1
46
47  power-domains:
48    maxItems: 1
49
50required:
51  - compatible
52  - reg
53  - interrupts
54  - clocks
55  - clock-frequency
56  - power-domains
57  - '#address-cells'
58  - '#size-cells'
59
60if:
61  properties:
62    compatible:
63      contains:
64        enum:
65          - renesas,riic-r9a07g044
66then:
67  required:
68    - resets
69
70unevaluatedProperties: false
71
72examples:
73  - |
74    #include <dt-bindings/clock/r7s72100-clock.h>
75    #include <dt-bindings/interrupt-controller/arm-gic.h>
76
77    i2c0: i2c@fcfee000 {
78            compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
79            reg = <0xfcfee000 0x44>;
80            interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
81                         <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
82                         <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
83                         <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
84                         <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
85                         <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
86                         <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
87                         <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
88            clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
89            clock-frequency = <100000>;
90            power-domains = <&cpg_clocks>;
91            #address-cells = <1>;
92            #size-cells = <0>;
93    };
94