1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/i2c/renesas,rcar-i2c.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Renesas R-Car I2C Controller 8 9maintainers: 10 - Wolfram Sang <wsa+renesas@sang-engineering.com> 11 12properties: 13 compatible: 14 oneOf: 15 - items: 16 - enum: 17 - renesas,i2c-r8a7778 # R-Car M1A 18 - renesas,i2c-r8a7779 # R-Car H1 19 - const: renesas,rcar-gen1-i2c # R-Car Gen1 20 21 - items: 22 - enum: 23 - renesas,i2c-r8a7742 # RZ/G1H 24 - renesas,i2c-r8a7743 # RZ/G1M 25 - renesas,i2c-r8a7744 # RZ/G1N 26 - renesas,i2c-r8a7745 # RZ/G1E 27 - renesas,i2c-r8a77470 # RZ/G1C 28 - renesas,i2c-r8a7790 # R-Car H2 29 - renesas,i2c-r8a7791 # R-Car M2-W 30 - renesas,i2c-r8a7792 # R-Car V2H 31 - renesas,i2c-r8a7793 # R-Car M2-N 32 - renesas,i2c-r8a7794 # R-Car E2 33 - const: renesas,rcar-gen2-i2c # R-Car Gen2 and RZ/G1 34 35 - items: 36 - enum: 37 - renesas,i2c-r8a774a1 # RZ/G2M 38 - renesas,i2c-r8a774b1 # RZ/G2N 39 - renesas,i2c-r8a774c0 # RZ/G2E 40 - renesas,i2c-r8a774e1 # RZ/G2H 41 - renesas,i2c-r8a7795 # R-Car H3 42 - renesas,i2c-r8a7796 # R-Car M3-W 43 - renesas,i2c-r8a77961 # R-Car M3-W+ 44 - renesas,i2c-r8a77965 # R-Car M3-N 45 - renesas,i2c-r8a77970 # R-Car V3M 46 - renesas,i2c-r8a77980 # R-Car V3H 47 - renesas,i2c-r8a77990 # R-Car E3 48 - renesas,i2c-r8a77995 # R-Car D3 49 - renesas,i2c-r8a779a0 # R-Car V3U 50 - const: renesas,rcar-gen3-i2c # R-Car Gen3 and RZ/G2 51 52 reg: 53 maxItems: 1 54 55 interrupts: 56 maxItems: 1 57 58 clock-frequency: 59 description: 60 Desired I2C bus clock frequency in Hz. The absence of this property 61 indicates the default frequency 100 kHz. 62 63 clocks: 64 maxItems: 1 65 66 power-domains: 67 maxItems: 1 68 69 resets: 70 maxItems: 1 71 72 dmas: 73 minItems: 2 74 maxItems: 4 75 description: 76 Must contain a list of pairs of references to DMA specifiers, one for 77 transmission, and one for reception. 78 79 dma-names: 80 minItems: 2 81 maxItems: 4 82 items: 83 enum: 84 - tx 85 - rx 86 87 i2c-scl-falling-time-ns: 88 default: 35 89 description: 90 Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C 91 specification. 92 93 i2c-scl-internal-delay-ns: 94 default: 50 95 description: 96 Number of nanoseconds the IP core additionally needs to setup SCL. 97 98 i2c-scl-rising-time-ns: 99 default: 200 100 description: 101 Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C 102 specification. 103 104required: 105 - compatible 106 - reg 107 - interrupts 108 - clocks 109 - power-domains 110 - '#address-cells' 111 - '#size-cells' 112 113allOf: 114 - $ref: /schemas/i2c/i2c-controller.yaml# 115 116 - if: 117 properties: 118 compatible: 119 contains: 120 enum: 121 - renesas,rcar-gen1-i2c 122 - renesas,rcar-gen2-i2c 123 then: 124 properties: 125 dmas: false 126 dma-names: false 127 128 - if: 129 properties: 130 compatible: 131 contains: 132 enum: 133 - renesas,rcar-gen2-i2c 134 - renesas,rcar-gen3-i2c 135 then: 136 required: 137 - resets 138 139unevaluatedProperties: false 140 141examples: 142 - | 143 #include <dt-bindings/clock/r8a7791-cpg-mssr.h> 144 #include <dt-bindings/interrupt-controller/arm-gic.h> 145 #include <dt-bindings/power/r8a7791-sysc.h> 146 147 i2c0: i2c@e6508000 { 148 #address-cells = <1>; 149 #size-cells = <0>; 150 compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; 151 reg = <0xe6508000 0x40>; 152 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 153 clock-frequency = <400000>; 154 clocks = <&cpg CPG_MOD 931>; 155 power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; 156 resets = <&cpg 931>; 157 i2c-scl-internal-delay-ns = <6>; 158 }; 159