1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/nvidia,tegra20-i2c.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7maintainers:
8  - Thierry Reding <thierry.reding@gmail.com>
9  - Jon Hunter <jonathanh@nvidia.com>
10
11title: NVIDIA Tegra I2C controller driver
12
13properties:
14  compatible:
15    oneOf:
16      - description: Tegra20 has 4 generic I2C controller. This can support
17          master and slave mode of I2C communication. The i2c-tegra driver
18          only support master mode of I2C communication. Driver of I2C
19          controller is only compatible with "nvidia,tegra20-i2c".
20        const: nvidia,tegra20-i2c
21      - description: Tegra20 has specific I2C controller called as DVC I2C
22          controller. This only support master mode of I2C communication.
23          Register interface/offset and interrupts handling are different than
24          generic I2C controller. Driver of DVC I2C controller is only
25          compatible with "nvidia,tegra20-i2c-dvc".
26        const: nvidia,tegra20-i2c-dvc
27      - description: |
28          Tegra30 has 5 generic I2C controller. This controller is very much
29          similar to Tegra20 I2C controller with additional feature: Continue
30          Transfer Support. This feature helps to implement M_NO_START as per
31          I2C core API transfer flags. Driver of I2C controller is compatible
32          with "nvidia,tegra30-i2c" to enable the continue transfer support.
33          This is also compatible with "nvidia,tegra20-i2c" without continue
34          transfer support.
35        items:
36          - const: nvidia,tegra30-i2c
37          - const: nvidia,tegra20-i2c
38      - description: |
39          Tegra114 has 5 generic I2C controllers. This controller is very much
40          similar to Tegra30 I2C controller with some hardware modification:
41            - Tegra30/Tegra20 I2C controller has 2 clock source called div-clk
42              and fast-clk. Tegra114 has only one clock source called as
43              div-clk and hence clock mechanism is changed in I2C controller.
44            - Tegra30/Tegra20 I2C controller has enabled per packet transfer
45              by default and there is no way to disable it. Tegra114 has this
46              interrupt disable by default and SW need to enable explicitly.
47          Due to above changes, Tegra114 I2C driver makes incompatible with
48          previous hardware driver. Hence, Tegra114 I2C controller is
49          compatible with "nvidia,tegra114-i2c".
50        const: nvidia,tegra114-i2c
51      - description: |
52          Tegra124 has 6 generic I2C controllers. These controllers are very
53          similar to those found on Tegra114 but also contain several hardware
54          improvements and new registers.
55        const: nvidia,tegra124-i2c
56      - description: |
57          Tegra210 has 6 generic I2C controllers. These controllers are very
58          similar to those found on Tegra124.
59        items:
60          - const: nvidia,tegra210-i2c
61          - const: nvidia,tegra124-i2c
62      - description: |
63          Tegra210 has one I2C controller that is on host1x bus and is part of
64          the VE power domain and typically used for camera use-cases. This VI
65          I2C controller is mostly compatible with the programming model of
66          the regular I2C controllers with a few exceptions. The I2C registers
67          start at an offset of 0xc00 (instead of 0), registers are 16 bytes
68          apart (rather than 4) and the controller does not support slave
69          mode.
70        const: nvidia,tegra210-i2c-vi
71      - description: |
72          Tegra186 has 9 generic I2C controllers, two of which are in the AON
73          (always-on) partition of the SoC. All of these controllers are very
74          similar to those found on Tegra210.
75        const: nvidia,tegra186-i2c
76      - description: |
77          Tegra194 has 8 generic I2C controllers, two of which are in the AON
78          (always-on) partition of the SoC. All of these controllers are very
79          similar to those found on Tegra186. However, these controllers have
80          support for 64 KiB transactions whereas earlier chips supported no
81          more than 4 KiB per transactions.
82        const: nvidia,tegra194-i2c
83
84  reg:
85    maxItems: 1
86
87  interrupts:
88    maxItems: 1
89
90  '#address-cells':
91    const: 1
92
93  '#size-cells':
94    const: 0
95
96  clocks:
97    minItems: 1
98    maxItems: 2
99
100  clock-names:
101    minItems: 1
102    maxItems: 2
103
104  resets:
105    items:
106      - description: module reset
107
108  reset-names:
109    items:
110      - const: i2c
111
112  dmas:
113    items:
114      - description: DMA channel for the reception FIFO
115      - description: DMA channel for the transmission FIFO
116
117  dma-names:
118    items:
119      - const: rx
120      - const: tx
121
122allOf:
123  - $ref: /schemas/i2c/i2c-controller.yaml
124  - if:
125      properties:
126        compatible:
127          contains:
128            enum:
129              - nvidia,tegra20-i2c
130              - nvidia,tegra30-i2c
131    then:
132      properties:
133        clock-names:
134          items:
135            - const: div-clk
136            - const: fast-clk
137
138  - if:
139      properties:
140        compatible:
141          contains:
142            const: nvidia,tegra114-i2c
143    then:
144      properties:
145        clock-names:
146          items:
147            - const: div-clk
148
149  - if:
150      properties:
151        compatible:
152          contains:
153            const: nvidia,tegra210-i2c
154    then:
155      properties:
156        clock-names:
157          items:
158            - const: div-clk
159
160  - if:
161      properties:
162        compatible:
163          contains:
164            const: nvidia,tegra210-i2c-vi
165    then:
166      properties:
167        clock-names:
168          items:
169            - const: div-clk
170            - const: slow
171        power-domains:
172          items:
173            - description: phandle to the VENC power domain
174
175unevaluatedProperties: false
176
177examples:
178  - |
179    i2c@7000c000 {
180        compatible = "nvidia,tegra20-i2c";
181        reg = <0x7000c000 0x100>;
182        interrupts = <0 38 0x04>;
183        clocks = <&tegra_car 12>, <&tegra_car 124>;
184        clock-names = "div-clk", "fast-clk";
185        resets = <&tegra_car 12>;
186        reset-names = "i2c";
187        dmas = <&apbdma 16>, <&apbdma 16>;
188        dma-names = "rx", "tx";
189
190        #address-cells = <1>;
191        #size-cells = <0>;
192    };
193