116c4c524SWolfram Sang* NXP PNX I2C Controller 216c4c524SWolfram Sang 316c4c524SWolfram SangRequired properties: 416c4c524SWolfram Sang 516c4c524SWolfram Sang - reg: Offset and length of the register set for the device 616c4c524SWolfram Sang - compatible: should be "nxp,pnx-i2c" 716c4c524SWolfram Sang - interrupts: configure one interrupt line 816c4c524SWolfram Sang - #address-cells: always 1 (for i2c addresses) 916c4c524SWolfram Sang - #size-cells: always 0 1016c4c524SWolfram Sang - interrupt-parent: the phandle for the interrupt controller that 1116c4c524SWolfram Sang services interrupts for this device. 1216c4c524SWolfram Sang 1316c4c524SWolfram SangOptional properties: 1416c4c524SWolfram Sang 1516c4c524SWolfram Sang - clock-frequency: desired I2C bus clock frequency in Hz, Default: 100000 Hz 1616c4c524SWolfram Sang 1716c4c524SWolfram SangExamples: 1816c4c524SWolfram Sang 1916c4c524SWolfram Sang i2c1: i2c@400a0000 { 2016c4c524SWolfram Sang compatible = "nxp,pnx-i2c"; 2116c4c524SWolfram Sang reg = <0x400a0000 0x100>; 2216c4c524SWolfram Sang interrupt-parent = <&mic>; 2316c4c524SWolfram Sang interrupts = <51 0>; 2416c4c524SWolfram Sang #address-cells = <1>; 2516c4c524SWolfram Sang #size-cells = <0>; 2616c4c524SWolfram Sang }; 2716c4c524SWolfram Sang 2816c4c524SWolfram Sang i2c2: i2c@400a8000 { 2916c4c524SWolfram Sang compatible = "nxp,pnx-i2c"; 3016c4c524SWolfram Sang reg = <0x400a8000 0x100>; 3116c4c524SWolfram Sang interrupt-parent = <&mic>; 3216c4c524SWolfram Sang interrupts = <50 0>; 3316c4c524SWolfram Sang #address-cells = <1>; 3416c4c524SWolfram Sang #size-cells = <0>; 3516c4c524SWolfram Sang clock-frequency = <100000>; 3616c4c524SWolfram Sang }; 37