116c4c524SWolfram Sang* NXP PNX I2C Controller
216c4c524SWolfram Sang
316c4c524SWolfram SangRequired properties:
416c4c524SWolfram Sang
516c4c524SWolfram Sang - reg: Offset and length of the register set for the device
616c4c524SWolfram Sang - compatible: should be "nxp,pnx-i2c"
716c4c524SWolfram Sang - interrupts: configure one interrupt line
816c4c524SWolfram Sang - #address-cells: always 1 (for i2c addresses)
916c4c524SWolfram Sang - #size-cells: always 0
1016c4c524SWolfram Sang
1116c4c524SWolfram SangOptional properties:
1216c4c524SWolfram Sang
1316c4c524SWolfram Sang - clock-frequency: desired I2C bus clock frequency in Hz, Default: 100000 Hz
1416c4c524SWolfram Sang
1516c4c524SWolfram SangExamples:
1616c4c524SWolfram Sang
1716c4c524SWolfram Sang	i2c1: i2c@400a0000 {
1816c4c524SWolfram Sang		compatible = "nxp,pnx-i2c";
1916c4c524SWolfram Sang		reg = <0x400a0000 0x100>;
2016c4c524SWolfram Sang		interrupt-parent = <&mic>;
2116c4c524SWolfram Sang		interrupts = <51 0>;
2216c4c524SWolfram Sang		#address-cells = <1>;
2316c4c524SWolfram Sang		#size-cells = <0>;
2416c4c524SWolfram Sang	};
2516c4c524SWolfram Sang
2616c4c524SWolfram Sang	i2c2: i2c@400a8000 {
2716c4c524SWolfram Sang		compatible = "nxp,pnx-i2c";
2816c4c524SWolfram Sang		reg = <0x400a8000 0x100>;
2916c4c524SWolfram Sang		interrupt-parent = <&mic>;
3016c4c524SWolfram Sang		interrupts = <50 0>;
3116c4c524SWolfram Sang		#address-cells = <1>;
3216c4c524SWolfram Sang		#size-cells = <0>;
3316c4c524SWolfram Sang		clock-frequency = <100000>;
3416c4c524SWolfram Sang	};
35