18f736816SThor Thayer* Altera I2C Controller 28f736816SThor Thayer* This is Altera's synthesizable logic block I2C Controller for use 38f736816SThor Thayer* in Altera's FPGAs. 48f736816SThor Thayer 58f736816SThor ThayerRequired properties : 68f736816SThor Thayer - compatible : should be "altr,softip-i2c-v1.0" 78f736816SThor Thayer - reg : Offset and length of the register set for the device 88f736816SThor Thayer - interrupts : <IRQ> where IRQ is the interrupt number. 98f736816SThor Thayer - clocks : phandle to input clock. 108f736816SThor Thayer - #address-cells = <1>; 118f736816SThor Thayer - #size-cells = <0>; 128f736816SThor Thayer 138f736816SThor ThayerRecommended properties : 148f736816SThor Thayer - clock-frequency : desired I2C bus clock frequency in Hz. 158f736816SThor Thayer 168f736816SThor ThayerOptional properties : 178f736816SThor Thayer - fifo-size : Size of the RX and TX FIFOs in bytes. 188f736816SThor Thayer - Child nodes conforming to i2c bus binding 198f736816SThor Thayer 208f736816SThor ThayerExample : 218f736816SThor Thayer 228f736816SThor Thayer i2c@100080000 { 238f736816SThor Thayer compatible = "altr,softip-i2c-v1.0"; 248f736816SThor Thayer reg = <0x00000001 0x00080000 0x00000040>; 258f736816SThor Thayer interrupt-parent = <&intc>; 268f736816SThor Thayer interrupts = <0 43 4>; 278f736816SThor Thayer clocks = <&clk_0>; 288f736816SThor Thayer clock-frequency = <100000>; 298f736816SThor Thayer #address-cells = <1>; 308f736816SThor Thayer #size-cells = <0>; 318f736816SThor Thayer fifo-size = <4>; 328f736816SThor Thayer 338f736816SThor Thayer eeprom@51 { 348f736816SThor Thayer compatible = "atmel,24c32"; 358f736816SThor Thayer reg = <0x51>; 368f736816SThor Thayer pagesize = <32>; 378f736816SThor Thayer }; 388f736816SThor Thayer }; 398f736816SThor Thayer 40