1aea37006SNobuhiro Iwamatsu# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2aea37006SNobuhiro Iwamatsu%YAML 1.2 3aea37006SNobuhiro Iwamatsu--- 4fc114c75SRob Herring$id: http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml# 5fc114c75SRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 6aea37006SNobuhiro Iwamatsu 7dd3cb467SAndrew Lunntitle: Cadence I2C controller 8aea37006SNobuhiro Iwamatsu 9aea37006SNobuhiro Iwamatsumaintainers: 10d5c421d2SMichal Simek - Michal Simek <michal.simek@amd.com> 11aea37006SNobuhiro Iwamatsu 12aea37006SNobuhiro IwamatsuallOf: 13aea37006SNobuhiro Iwamatsu - $ref: /schemas/i2c/i2c-controller.yaml# 14aea37006SNobuhiro Iwamatsu 15aea37006SNobuhiro Iwamatsuproperties: 16aea37006SNobuhiro Iwamatsu compatible: 17aea37006SNobuhiro Iwamatsu enum: 18aea37006SNobuhiro Iwamatsu - cdns,i2c-r1p10 # cadence i2c controller version 1.0 19aea37006SNobuhiro Iwamatsu - cdns,i2c-r1p14 # cadence i2c controller version 1.4 20aea37006SNobuhiro Iwamatsu 21aea37006SNobuhiro Iwamatsu reg: 22aea37006SNobuhiro Iwamatsu maxItems: 1 23aea37006SNobuhiro Iwamatsu 24aea37006SNobuhiro Iwamatsu clocks: 25aea37006SNobuhiro Iwamatsu minItems: 1 26aea37006SNobuhiro Iwamatsu 2784554609SLars-Peter Clausen resets: 2884554609SLars-Peter Clausen maxItems: 1 2984554609SLars-Peter Clausen 30aea37006SNobuhiro Iwamatsu interrupts: 31aea37006SNobuhiro Iwamatsu maxItems: 1 32aea37006SNobuhiro Iwamatsu 33aea37006SNobuhiro Iwamatsu clock-frequency: 34aea37006SNobuhiro Iwamatsu minimum: 1 35aea37006SNobuhiro Iwamatsu maximum: 400000 36aea37006SNobuhiro Iwamatsu description: | 37aea37006SNobuhiro Iwamatsu Desired operating frequency, in Hz, of the bus. 38aea37006SNobuhiro Iwamatsu 39aea37006SNobuhiro Iwamatsu clock-name: 40aea37006SNobuhiro Iwamatsu const: pclk 41aea37006SNobuhiro Iwamatsu description: | 42aea37006SNobuhiro Iwamatsu Input clock name. 43aea37006SNobuhiro Iwamatsu 446ff0ddb3SLars-Peter Clausen fifo-depth: 456ff0ddb3SLars-Peter Clausen description: 466ff0ddb3SLars-Peter Clausen Size of the data FIFO in bytes. 476ff0ddb3SLars-Peter Clausen $ref: /schemas/types.yaml#/definitions/uint32 486ff0ddb3SLars-Peter Clausen default: 16 496ff0ddb3SLars-Peter Clausen enum: [2, 4, 8, 16, 32, 64, 128, 256] 506ff0ddb3SLars-Peter Clausen 51*55f5cd61SMichal Simek power-domains: 52*55f5cd61SMichal Simek maxItems: 1 53*55f5cd61SMichal Simek 54aea37006SNobuhiro Iwamatsurequired: 55aea37006SNobuhiro Iwamatsu - compatible 56aea37006SNobuhiro Iwamatsu - reg 57aea37006SNobuhiro Iwamatsu - clocks 58aea37006SNobuhiro Iwamatsu - interrupts 59aea37006SNobuhiro Iwamatsu 606fdc6e23SRob HerringunevaluatedProperties: false 616fdc6e23SRob Herring 62aea37006SNobuhiro Iwamatsuexamples: 63aea37006SNobuhiro Iwamatsu - | 64aea37006SNobuhiro Iwamatsu #include <dt-bindings/interrupt-controller/arm-gic.h> 65aea37006SNobuhiro Iwamatsu i2c@e0004000 { 66aea37006SNobuhiro Iwamatsu compatible = "cdns,i2c-r1p10"; 67aea37006SNobuhiro Iwamatsu clocks = <&clkc 38>; 6884554609SLars-Peter Clausen resets = <&rstc 288>; 69aea37006SNobuhiro Iwamatsu interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 70aea37006SNobuhiro Iwamatsu reg = <0xe0004000 0x1000>; 71aea37006SNobuhiro Iwamatsu clock-frequency = <400000>; 72aea37006SNobuhiro Iwamatsu #address-cells = <1>; 73aea37006SNobuhiro Iwamatsu #size-cells = <0>; 746ff0ddb3SLars-Peter Clausen fifo-depth = <8>; 75aea37006SNobuhiro Iwamatsu }; 76