1# SPDX-License-Identifier: GPL-2.0-only 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: ARM Mali Utgard GPU 8 9maintainers: 10 - Rob Herring <robh@kernel.org> 11 - Maxime Ripard <mripard@kernel.org> 12 - Heiko Stuebner <heiko@sntech.de> 13 14properties: 15 $nodename: 16 pattern: '^gpu@[a-f0-9]+$' 17 compatible: 18 oneOf: 19 - items: 20 - const: allwinner,sun8i-a23-mali 21 - const: allwinner,sun7i-a20-mali 22 - const: arm,mali-400 23 - items: 24 - enum: 25 - allwinner,sun4i-a10-mali 26 - allwinner,sun7i-a20-mali 27 - allwinner,sun8i-h3-mali 28 - allwinner,sun8i-r40-mali 29 - allwinner,sun50i-a64-mali 30 - rockchip,rk3036-mali 31 - rockchip,rk3066-mali 32 - rockchip,rk3188-mali 33 - rockchip,rk3228-mali 34 - samsung,exynos4210-mali 35 - stericsson,db8500-mali 36 - xlnx,zynqmp-mali 37 - const: arm,mali-400 38 - items: 39 - enum: 40 - allwinner,sun50i-h5-mali 41 - amlogic,meson8-mali 42 - amlogic,meson8b-mali 43 - amlogic,meson-gxbb-mali 44 - amlogic,meson-gxl-mali 45 - hisilicon,hi6220-mali 46 - mediatek,mt7623-mali 47 - rockchip,rk3328-mali 48 - const: arm,mali-450 49 50 # "arm,mali-300" 51 52 reg: 53 maxItems: 1 54 55 interrupts: 56 minItems: 4 57 maxItems: 20 58 59 interrupt-names: 60 allOf: 61 - additionalItems: true 62 minItems: 4 63 maxItems: 20 64 items: 65 # At least enforce the first 2 interrupts 66 - const: gp 67 - const: gpmmu 68 - items: 69 # Not ideal as any order and combination are allowed 70 enum: 71 - gp # Geometry Processor interrupt 72 - gpmmu # Geometry Processor MMU interrupt 73 - pp # Pixel Processor broadcast interrupt (mali-450 only) 74 - pp0 # Pixel Processor X interrupt (X from 0 to 7) 75 - ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7) 76 - pp1 77 - ppmmu1 78 - pp2 79 - ppmmu2 80 - pp3 81 - ppmmu3 82 - pp4 83 - ppmmu4 84 - pp5 85 - ppmmu5 86 - pp6 87 - ppmmu6 88 - pp7 89 - ppmmu7 90 - pmu # Power Management Unit interrupt (optional) 91 - combined # stericsson,db8500-mali only 92 93 clocks: 94 maxItems: 2 95 96 clock-names: 97 items: 98 - const: bus 99 - const: core 100 101 memory-region: true 102 103 mali-supply: true 104 105 opp-table: 106 type: object 107 108 power-domains: 109 maxItems: 1 110 111 resets: 112 maxItems: 1 113 114 operating-points-v2: true 115 116 "#cooling-cells": 117 const: 2 118 119required: 120 - compatible 121 - reg 122 - interrupts 123 - interrupt-names 124 - clocks 125 - clock-names 126 127additionalProperties: false 128 129allOf: 130 - if: 131 properties: 132 compatible: 133 contains: 134 enum: 135 - allwinner,sun4i-a10-mali 136 - allwinner,sun7i-a20-mali 137 - allwinner,sun8i-r40-mali 138 - allwinner,sun50i-a64-mali 139 - allwinner,sun50i-h5-mali 140 - amlogic,meson8-mali 141 - amlogic,meson8b-mali 142 - hisilicon,hi6220-mali 143 - mediatek,mt7623-mali 144 - rockchip,rk3036-mali 145 - rockchip,rk3066-mali 146 - rockchip,rk3188-mali 147 - rockchip,rk3228-mali 148 - rockchip,rk3328-mali 149 then: 150 required: 151 - resets 152 153examples: 154 - | 155 #include <dt-bindings/interrupt-controller/irq.h> 156 #include <dt-bindings/interrupt-controller/arm-gic.h> 157 158 mali: gpu@1c40000 { 159 compatible = "allwinner,sun7i-a20-mali", "arm,mali-400"; 160 reg = <0x01c40000 0x10000>; 161 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 168 interrupt-names = "gp", 169 "gpmmu", 170 "pp0", 171 "ppmmu0", 172 "pp1", 173 "ppmmu1", 174 "pmu"; 175 clocks = <&ccu 1>, <&ccu 2>; 176 clock-names = "bus", "core"; 177 resets = <&ccu 1>; 178 #cooling-cells = <2>; 179 }; 180 181... 182