1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/gpu/arm,mali-utgard.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM Mali Utgard GPU
8
9maintainers:
10  - Rob Herring <robh@kernel.org>
11  - Maxime Ripard <maxime.ripard@free-electrons.com>
12  - Heiko Stuebner <heiko@sntech.de>
13
14properties:
15  $nodename:
16    pattern: '^gpu@[a-f0-9]+$'
17  compatible:
18    oneOf:
19      - items:
20          - const: allwinner,sun8i-a23-mali
21          - const: allwinner,sun7i-a20-mali
22          - const: arm,mali-400
23      - items:
24          - enum:
25              - allwinner,sun4i-a10-mali
26              - allwinner,sun7i-a20-mali
27              - allwinner,sun8i-h3-mali
28              - allwinner,sun50i-a64-mali
29              - rockchip,rk3036-mali
30              - rockchip,rk3066-mali
31              - rockchip,rk3188-mali
32              - rockchip,rk3228-mali
33              - samsung,exynos4210-mali
34              - stericsson,db8500-mali
35          - const: arm,mali-400
36      - items:
37          - enum:
38              - allwinner,sun50i-h5-mali
39              - amlogic,meson8-mali
40              - amlogic,meson8b-mali
41              - amlogic,meson-gxbb-mali
42              - amlogic,meson-gxl-mali
43              - hisilicon,hi6220-mali
44              - rockchip,rk3328-mali
45          - const: arm,mali-450
46
47      # "arm,mali-300"
48
49  reg:
50    maxItems: 1
51
52  interrupts:
53    minItems: 4
54    maxItems: 20
55
56  interrupt-names:
57    allOf:
58      - additionalItems: true
59        minItems: 4
60        maxItems: 20
61        items:
62          # At least enforce the first 2 interrupts
63          - const: gp
64          - const: gpmmu
65      - items:
66          # Not ideal as any order and combination are allowed
67          enum:
68            - gp        # Geometry Processor interrupt
69            - gpmmu     # Geometry Processor MMU interrupt
70            - pp        # Pixel Processor broadcast interrupt (mali-450 only)
71            - pp0       # Pixel Processor X interrupt (X from 0 to 7)
72            - ppmmu0    # Pixel Processor X MMU interrupt (X from 0 to 7)
73            - pp1
74            - ppmmu1
75            - pp2
76            - ppmmu2
77            - pp3
78            - ppmmu3
79            - pp4
80            - ppmmu4
81            - pp5
82            - ppmmu5
83            - pp6
84            - ppmmu6
85            - pp7
86            - ppmmu7
87            - pmu       # Power Management Unit interrupt (optional)
88            - combined  # stericsson,db8500-mali only
89
90  clocks:
91    maxItems: 2
92
93  clock-names:
94    items:
95      - const: bus
96      - const: core
97
98  memory-region: true
99
100  mali-supply: true
101
102  power-domains:
103    maxItems: 1
104
105  resets:
106    maxItems: 1
107
108  operating-points-v2: true
109
110required:
111  - compatible
112  - reg
113  - interrupts
114  - interrupt-names
115  - clocks
116  - clock-names
117
118additionalProperties: false
119
120allOf:
121  - if:
122      properties:
123        compatible:
124          contains:
125            enum:
126              - allwinner,sun4i-a10-mali
127              - allwinner,sun7i-a20-mali
128              - allwinner,sun50i-a64-mali
129              - allwinner,sun50i-h5-mali
130              - amlogic,meson8-mali
131              - amlogic,meson8b-mali
132              - hisilicon,hi6220-mali
133              - rockchip,rk3036-mali
134              - rockchip,rk3066-mali
135              - rockchip,rk3188-mali
136              - rockchip,rk3228-mali
137              - rockchip,rk3328-mali
138    then:
139      required:
140        - resets
141
142examples:
143  - |
144    #include <dt-bindings/interrupt-controller/irq.h>
145    #include <dt-bindings/interrupt-controller/arm-gic.h>
146
147    mali: gpu@1c40000 {
148      compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
149      reg = <0x01c40000 0x10000>;
150      interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
151             <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
152             <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
153             <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
154             <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
155             <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
156             <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
157      interrupt-names = "gp",
158            "gpmmu",
159            "pp0",
160            "ppmmu0",
161            "pp1",
162            "ppmmu1",
163            "pmu";
164      clocks = <&ccu 1>, <&ccu 2>;
165      clock-names = "bus", "core";
166      resets = <&ccu 1>;
167    };
168
169...
170