1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright 2022 Unisoc Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/gpio/sprd,gpio.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: Unisoc GPIO controller
9
10maintainers:
11  - Orson Zhai <orsonzhai@gmail.com>
12  - Baolin Wang <baolin.wang7@gmail.com>
13  - Chunyan Zhang <zhang.lyra@gmail.com>
14
15description: |
16  The controller's registers are organized as sets of sixteen 16-bit
17  registers with each set controlling a bank of up to 16 pins. A single
18  interrupt is shared for all of the banks handled by the controller.
19
20properties:
21  compatible:
22    const: sprd,sc9860-gpio
23
24  reg:
25    maxItems: 1
26
27  gpio-controller: true
28
29  "#gpio-cells":
30    const: 2
31
32  interrupt-controller: true
33
34  "#interrupt-cells":
35    const: 2
36
37  interrupts:
38    maxItems: 1
39    description: The interrupt shared by all GPIO lines for this controller.
40
41required:
42  - compatible
43  - reg
44  - gpio-controller
45  - "#gpio-cells"
46  - interrupt-controller
47  - "#interrupt-cells"
48  - interrupts
49
50additionalProperties: false
51
52examples:
53  - |
54    #include <dt-bindings/interrupt-controller/arm-gic.h>
55
56    soc {
57        #address-cells = <2>;
58        #size-cells = <2>;
59
60        ap_gpio: gpio@40280000 {
61            compatible = "sprd,sc9860-gpio";
62            reg = <0 0x40280000 0 0x1000>;
63            gpio-controller;
64            #gpio-cells = <2>;
65            interrupt-controller;
66            #interrupt-cells = <2>;
67            interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
68        };
69    };
70...
71