1*59184e12SChunyan Zhang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*59184e12SChunyan Zhang# Copyright 2022 Unisoc Inc. 3*59184e12SChunyan Zhang%YAML 1.2 4*59184e12SChunyan Zhang--- 5*59184e12SChunyan Zhang$id: http://devicetree.org/schemas/gpio/sprd,gpio.yaml# 6*59184e12SChunyan Zhang$schema: http://devicetree.org/meta-schemas/core.yaml# 7*59184e12SChunyan Zhang 8*59184e12SChunyan Zhangtitle: Unisoc GPIO controller 9*59184e12SChunyan Zhang 10*59184e12SChunyan Zhangmaintainers: 11*59184e12SChunyan Zhang - Orson Zhai <orsonzhai@gmail.com> 12*59184e12SChunyan Zhang - Baolin Wang <baolin.wang7@gmail.com> 13*59184e12SChunyan Zhang - Chunyan Zhang <zhang.lyra@gmail.com> 14*59184e12SChunyan Zhang 15*59184e12SChunyan Zhangdescription: | 16*59184e12SChunyan Zhang The controller's registers are organized as sets of sixteen 16-bit 17*59184e12SChunyan Zhang registers with each set controlling a bank of up to 16 pins. A single 18*59184e12SChunyan Zhang interrupt is shared for all of the banks handled by the controller. 19*59184e12SChunyan Zhang 20*59184e12SChunyan Zhangproperties: 21*59184e12SChunyan Zhang compatible: 22*59184e12SChunyan Zhang const: sprd,sc9860-gpio 23*59184e12SChunyan Zhang 24*59184e12SChunyan Zhang reg: 25*59184e12SChunyan Zhang maxItems: 1 26*59184e12SChunyan Zhang 27*59184e12SChunyan Zhang gpio-controller: true 28*59184e12SChunyan Zhang 29*59184e12SChunyan Zhang "#gpio-cells": 30*59184e12SChunyan Zhang const: 2 31*59184e12SChunyan Zhang 32*59184e12SChunyan Zhang interrupt-controller: true 33*59184e12SChunyan Zhang 34*59184e12SChunyan Zhang "#interrupt-cells": 35*59184e12SChunyan Zhang const: 2 36*59184e12SChunyan Zhang 37*59184e12SChunyan Zhang interrupts: 38*59184e12SChunyan Zhang maxItems: 1 39*59184e12SChunyan Zhang description: The interrupt shared by all GPIO lines for this controller. 40*59184e12SChunyan Zhang 41*59184e12SChunyan Zhangrequired: 42*59184e12SChunyan Zhang - compatible 43*59184e12SChunyan Zhang - reg 44*59184e12SChunyan Zhang - gpio-controller 45*59184e12SChunyan Zhang - "#gpio-cells" 46*59184e12SChunyan Zhang - interrupt-controller 47*59184e12SChunyan Zhang - "#interrupt-cells" 48*59184e12SChunyan Zhang - interrupts 49*59184e12SChunyan Zhang 50*59184e12SChunyan ZhangadditionalProperties: false 51*59184e12SChunyan Zhang 52*59184e12SChunyan Zhangexamples: 53*59184e12SChunyan Zhang - | 54*59184e12SChunyan Zhang #include <dt-bindings/interrupt-controller/arm-gic.h> 55*59184e12SChunyan Zhang 56*59184e12SChunyan Zhang soc { 57*59184e12SChunyan Zhang #address-cells = <2>; 58*59184e12SChunyan Zhang #size-cells = <2>; 59*59184e12SChunyan Zhang 60*59184e12SChunyan Zhang ap_gpio: gpio@40280000 { 61*59184e12SChunyan Zhang compatible = "sprd,sc9860-gpio"; 62*59184e12SChunyan Zhang reg = <0 0x40280000 0 0x1000>; 63*59184e12SChunyan Zhang gpio-controller; 64*59184e12SChunyan Zhang #gpio-cells = <2>; 65*59184e12SChunyan Zhang interrupt-controller; 66*59184e12SChunyan Zhang #interrupt-cells = <2>; 67*59184e12SChunyan Zhang interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 68*59184e12SChunyan Zhang }; 69*59184e12SChunyan Zhang }; 70*59184e12SChunyan Zhang... 71