1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/gpio/socionext,uniphier-gpio.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: UniPhier GPIO controller 8 9maintainers: 10 - Masahiro Yamada <yamada.masahiro@socionext.com> 11 12properties: 13 $nodename: 14 pattern: "^gpio@[0-9a-f]+$" 15 16 compatible: 17 const: socionext,uniphier-gpio 18 19 reg: 20 maxItems: 1 21 22 gpio-controller: true 23 24 "#gpio-cells": 25 const: 2 26 27 interrupt-controller: true 28 29 "#interrupt-cells": 30 description: | 31 The first cell defines the interrupt number. 32 The second cell bits[3:0] is used to specify trigger type as follows: 33 1 = low-to-high edge triggered 34 2 = high-to-low edge triggered 35 4 = active high level-sensitive 36 8 = active low level-sensitive 37 Valid combinations are 1, 2, 3, 4, 8. 38 const: 2 39 40 ngpios: 41 minimum: 0 42 maximum: 512 43 44 gpio-ranges-group-names: 45 $ref: /schemas/types.yaml#/definitions/string-array 46 47 socionext,interrupt-ranges: 48 description: | 49 Specifies an interrupt number mapping between this GPIO controller and 50 its interrupt parent, in the form of arbitrary number of 51 <child-interrupt-base parent-interrupt-base length> triplets. 52 $ref: /schemas/types.yaml#/definitions/uint32-matrix 53 54required: 55 - compatible 56 - reg 57 - gpio-controller 58 - "#gpio-cells" 59 - interrupt-controller 60 - "#interrupt-cells" 61 - ngpios 62 - gpio-ranges 63 - socionext,interrupt-ranges 64 65examples: 66 - | 67 #include <dt-bindings/gpio/gpio.h> 68 #include <dt-bindings/gpio/uniphier-gpio.h> 69 70 gpio: gpio@55000000 { 71 compatible = "socionext,uniphier-gpio"; 72 reg = <0x55000000 0x200>; 73 interrupt-parent = <&aidet>; 74 interrupt-controller; 75 #interrupt-cells = <2>; 76 gpio-controller; 77 #gpio-cells = <2>; 78 gpio-ranges = <&pinctrl 0 0 0>; 79 gpio-ranges-group-names = "gpio_range"; 80 ngpios = <248>; 81 socionext,interrupt-ranges = <0 48 16>, <16 154 5>, <21 217 3>; 82 }; 83 84 // Consumer: 85 // Please note UNIPHIER_GPIO_PORT(29, 4) represents PORT294 in the SoC 86 // document. Unfortunately, only the one's place is octal in the port 87 // numbering. (That is, PORT 8, 9, 18, 19, 28, 29, ... do not exist.) 88 // UNIPHIER_GPIO_PORT() is a helper macro to calculate 29 * 8 + 4. 89 sdhci0_pwrseq { 90 compatible = "mmc-pwrseq-emmc"; 91 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(29, 4) GPIO_ACTIVE_LOW>; 92 }; 93