1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip GPIO bank
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12properties:
13  compatible:
14    enum:
15      - rockchip,gpio-bank
16      - rockchip,rk3188-gpio-bank0
17
18  reg:
19    maxItems: 1
20
21  interrupts:
22    maxItems: 1
23
24  clocks:
25    minItems: 1
26    items:
27      - description: APB interface clock source
28      - description: GPIO debounce reference clock source
29
30  gpio-controller: true
31
32  "#gpio-cells":
33    const: 2
34
35  interrupt-controller: true
36
37  "#interrupt-cells":
38    const: 2
39
40required:
41  - compatible
42  - reg
43  - interrupts
44  - clocks
45  - gpio-controller
46  - "#gpio-cells"
47  - interrupt-controller
48  - "#interrupt-cells"
49
50additionalProperties: false
51
52examples:
53  - |
54    #include <dt-bindings/interrupt-controller/arm-gic.h>
55    pinctrl: pinctrl {
56      #address-cells = <1>;
57      #size-cells = <1>;
58      ranges;
59
60      gpio0: gpio@2000a000 {
61        compatible = "rockchip,rk3188-gpio-bank0";
62        reg = <0x2000a000 0x100>;
63        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
64        clocks = <&clk_gates8 9>;
65
66        gpio-controller;
67        #gpio-cells = <2>;
68
69        interrupt-controller;
70        #interrupt-cells = <2>;
71      };
72
73      gpio1: gpio@2003c000 {
74        compatible = "rockchip,gpio-bank";
75        reg = <0x2003c000 0x100>;
76        interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
77        clocks = <&clk_gates8 10>;
78
79        gpio-controller;
80        #gpio-cells = <2>;
81
82        interrupt-controller;
83        #interrupt-cells = <2>;
84      };
85    };
86