1e92935e1SRoland StiggeNXP LPC32xx SoC GPIO controller 2e92935e1SRoland Stigge 3e92935e1SRoland StiggeRequired properties: 4e92935e1SRoland Stigge- compatible: must be "nxp,lpc3220-gpio" 5e92935e1SRoland Stigge- reg: Physical base address and length of the controller's registers. 6e92935e1SRoland Stigge- gpio-controller: Marks the device node as a GPIO controller. 7e92935e1SRoland Stigge- #gpio-cells: Should be 3: 8e92935e1SRoland Stigge 1) bank: 9e92935e1SRoland Stigge 0: GPIO P0 10e92935e1SRoland Stigge 1: GPIO P1 11e92935e1SRoland Stigge 2: GPIO P2 12e92935e1SRoland Stigge 3: GPIO P3 13e92935e1SRoland Stigge 4: GPI P3 14e92935e1SRoland Stigge 5: GPO P3 15e92935e1SRoland Stigge 2) pin number 16e92935e1SRoland Stigge 3) optional parameters: 17e92935e1SRoland Stigge - bit 0 specifies polarity (0 for normal, 1 for inverted) 18e92935e1SRoland Stigge- reg: Index of the GPIO group 19e92935e1SRoland Stigge 20e92935e1SRoland StiggeExample: 21e92935e1SRoland Stigge 22e92935e1SRoland Stigge gpio: gpio@40028000 { 23e92935e1SRoland Stigge compatible = "nxp,lpc3220-gpio"; 24e92935e1SRoland Stigge reg = <0x40028000 0x1000>; 25e92935e1SRoland Stigge gpio-controller; 26e92935e1SRoland Stigge #gpio-cells = <3>; /* bank, pin, flags */ 27e92935e1SRoland Stigge }; 28e92935e1SRoland Stigge 29e92935e1SRoland Stigge leds { 30e92935e1SRoland Stigge compatible = "gpio-leds"; 31e92935e1SRoland Stigge 32e92935e1SRoland Stigge led0 { 33e92935e1SRoland Stigge gpios = <&gpio 5 1 1>; /* GPO_P3 1, active low */ 34e92935e1SRoland Stigge linux,default-trigger = "heartbeat"; 35e92935e1SRoland Stigge default-state = "off"; 36e92935e1SRoland Stigge }; 37e92935e1SRoland Stigge 38e92935e1SRoland Stigge led1 { 39e92935e1SRoland Stigge gpios = <&gpio 5 14 1>; /* GPO_P3 14, active low */ 40e92935e1SRoland Stigge linux,default-trigger = "timer"; 41e92935e1SRoland Stigge default-state = "off"; 42e92935e1SRoland Stigge }; 43e92935e1SRoland Stigge }; 44