1Specifying GPIO information for devices 2============================================ 3 41) gpios property 5----------------- 6 7Nodes that makes use of GPIOs should specify them using one or more 8properties, each containing a 'gpio-list': 9 10 gpio-list ::= <single-gpio> [gpio-list] 11 single-gpio ::= <gpio-phandle> <gpio-specifier> 12 gpio-phandle : phandle to gpio controller node 13 gpio-specifier : Array of #gpio-cells specifying specific gpio 14 (controller specific) 15 16GPIO properties should be named "[<name>-]gpios", with <name> being the purpose 17of this GPIO for the device. While a non-existent <name> is considered valid 18for compatibility reasons (resolving to the "gpios" property), it is not allowed 19for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old 20bindings use it, but are only supported for compatibility reasons and should not 21be used for newer bindings since it has been deprecated. 22 23GPIO properties can contain one or more GPIO phandles, but only in exceptional 24cases should they contain more than one. If your device uses several GPIOs with 25distinct functions, reference each of them under its own property, giving it a 26meaningful name. The only case where an array of GPIOs is accepted is when 27several GPIOs serve the same function (e.g. a parallel data line). 28 29The exact purpose of each gpios property must be documented in the device tree 30binding of the device. 31 32The following example could be used to describe GPIO pins used as device enable 33and bit-banged data signals: 34 35 gpio1: gpio1 { 36 gpio-controller 37 #gpio-cells = <2>; 38 }; 39 gpio2: gpio2 { 40 gpio-controller 41 #gpio-cells = <1>; 42 }; 43 [...] 44 45 enable-gpios = <&gpio2 2>; 46 data-gpios = <&gpio1 12 0>, 47 <&gpio1 13 0>, 48 <&gpio1 14 0>, 49 <&gpio1 15 0>; 50 51Note that gpio-specifier length is controller dependent. In the 52above example, &gpio1 uses 2 cells to specify a gpio, while &gpio2 53only uses one. 54 55gpio-specifier may encode: bank, pin position inside the bank, 56whether pin is open-drain and whether pin is logically inverted. 57 58Exact meaning of each specifier cell is controller specific, and must 59be documented in the device tree binding for the device. 60 61Most controllers are however specifying a generic flag bitfield 62in the last cell, so for these, use the macros defined in 63include/dt-bindings/gpio/gpio.h whenever possible: 64 65Example of a node using GPIOs: 66 67 node { 68 enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>; 69 }; 70 71GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes 72GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller. 73 74Optional standard bitfield specifiers for the last cell: 75 76- Bit 0: 0 means active high, 1 means active low 77- Bit 1: 0 mean push-pull wiring, see: 78 https://en.wikipedia.org/wiki/Push-pull_output 79 1 means single-ended wiring, see: 80 https://en.wikipedia.org/wiki/Single-ended_triode 81- Bit 2: 0 means open-source, 1 means open drain, see: 82 https://en.wikipedia.org/wiki/Open_collector 83- Bit 3: 0 means the output should be maintained during sleep/low-power mode 84 1 means the output state can be lost during sleep/low-power mode 85 861.1) GPIO specifier best practices 87---------------------------------- 88 89A gpio-specifier should contain a flag indicating the GPIO polarity; active- 90high or active-low. If it does, the following best practices should be 91followed: 92 93The gpio-specifier's polarity flag should represent the physical level at the 94GPIO controller that achieves (or represents, for inputs) a logically asserted 95value at the device. The exact definition of logically asserted should be 96defined by the binding for the device. If the board inverts the signal between 97the GPIO controller and the device, then the gpio-specifier will represent the 98opposite physical level than the signal at the device's pin. 99 100When the device's signal polarity is configurable, the binding for the 101device must either: 102 103a) Define a single static polarity for the signal, with the expectation that 104any software using that binding would statically program the device to use 105that signal polarity. 106 107The static choice of polarity may be either: 108 109a1) (Preferred) Dictated by a binding-specific DT property. 110 111or: 112 113a2) Defined statically by the DT binding itself. 114 115In particular, the polarity cannot be derived from the gpio-specifier, since 116that would prevent the DT from separately representing the two orthogonal 117concepts of configurable signal polarity in the device, and possible board- 118level signal inversion. 119 120or: 121 122b) Pick a single option for device signal polarity, and document this choice 123in the binding. The gpio-specifier should represent the polarity of the signal 124(at the GPIO controller) assuming that the device is configured for this 125particular signal polarity choice. If software chooses to program the device 126to generate or receive a signal of the opposite polarity, software will be 127responsible for correctly interpreting (inverting) the GPIO signal at the GPIO 128controller. 129 1302) gpio-controller nodes 131------------------------ 132 133Every GPIO controller node must contain both an empty "gpio-controller" 134property, and a #gpio-cells integer property, which indicates the number of 135cells in a gpio-specifier. 136 137Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an 138instance of a hardware IP core on a silicon die, usually exposed to the 139programmer as a coherent range of I/O addresses. Usually each such bank is 140exposed in the device tree as an individual gpio-controller node, reflecting 141the fact that the hardware was synthesized by reusing the same IP block a 142few times over. 143 144Optionally, a GPIO controller may have a "ngpios" property. This property 145indicates the number of in-use slots of available slots for GPIOs. The 146typical example is something like this: the hardware register is 32 bits 147wide, but only 18 of the bits have a physical counterpart. The driver is 148generally written so that all 32 bits can be used, but the IP block is reused 149in a lot of designs, some using all 32 bits, some using 18 and some using 15012. In this case, setting "ngpios = <18>;" informs the driver that only the 151first 18 GPIOs, at local offset 0 .. 17, are in use. 152 153If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an 154additional set of tuples is needed to specify which GPIOs are unusable, with 155the gpio-reserved-ranges binding. This property indicates the start and size 156of the GPIOs that can't be used. 157 158Optionally, a GPIO controller may have a "gpio-line-names" property. This is 159an array of strings defining the names of the GPIO lines going out of the 160GPIO controller. This name should be the most meaningful producer name 161for the system, such as a rail name indicating the usage. Package names 162such as pin name are discouraged: such lines have opaque names (since they 163are by definition generic purpose) and such names are usually not very 164helpful. For example "MMC-CD", "Red LED Vdd" and "ethernet reset" are 165reasonable line names as they describe what the line is used for. "GPIO0" 166is not a good name to give to a GPIO line. Placeholders are discouraged: 167rather use the "" (blank string) if the use of the GPIO line is undefined 168in your design. The names are assigned starting from line offset 0 from 169left to right from the passed array. An incomplete array (where the number 170of passed named are less than ngpios) will still be used up until the last 171provided valid line index. 172 173Example: 174 175gpio-controller@00000000 { 176 compatible = "foo"; 177 reg = <0x00000000 0x1000>; 178 gpio-controller; 179 #gpio-cells = <2>; 180 ngpios = <18>; 181 gpio-reserved-ranges = <0 4>, <12 2>; 182 gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R", 183 "LED G", "LED B", "Col A", "Col B", "Col C", "Col D", 184 "Row A", "Row B", "Row C", "Row D", "NMI button", 185 "poweroff", "reset"; 186} 187 188The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism 189providing automatic GPIO request and configuration as part of the 190gpio-controller's driver probe function. 191 192Each GPIO hog definition is represented as a child node of the GPIO controller. 193Required properties: 194- gpio-hog: A property specifying that this child node represents a GPIO hog. 195- gpios: Store the GPIO information (id, flags, ...) for each GPIO to 196 affect. Shall contain an integer multiple of the number of cells 197 specified in its parent node (GPIO controller node). 198Only one of the following properties scanned in the order shown below. 199This means that when multiple properties are present they will be searched 200in the order presented below and the first match is taken as the intended 201configuration. 202- input: A property specifying to set the GPIO direction as input. 203- output-low A property specifying to set the GPIO direction as output with 204 the value low. 205- output-high A property specifying to set the GPIO direction as output with 206 the value high. 207 208Optional properties: 209- line-name: The GPIO label name. If not present the node name is used. 210 211Example of two SOC GPIO banks defined as gpio-controller nodes: 212 213 qe_pio_a: gpio-controller@1400 { 214 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank"; 215 reg = <0x1400 0x18>; 216 gpio-controller; 217 #gpio-cells = <2>; 218 219 line_b { 220 gpio-hog; 221 gpios = <6 0>; 222 output-low; 223 line-name = "foo-bar-gpio"; 224 }; 225 }; 226 227 qe_pio_e: gpio-controller@1460 { 228 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; 229 reg = <0x1460 0x18>; 230 gpio-controller; 231 #gpio-cells = <2>; 232 }; 233 2342.1) gpio- and pin-controller interaction 235----------------------------------------- 236 237Some or all of the GPIOs provided by a GPIO controller may be routed to pins 238on the package via a pin controller. This allows muxing those pins between 239GPIO and other functions. 240 241It is useful to represent which GPIOs correspond to which pins on which pin 242controllers. The gpio-ranges property described below represents this, and 243contains information structures as follows: 244 245 gpio-range-list ::= <single-gpio-range> [gpio-range-list] 246 single-gpio-range ::= <numeric-gpio-range> | <named-gpio-range> 247 numeric-gpio-range ::= 248 <pinctrl-phandle> <gpio-base> <pinctrl-base> <count> 249 named-gpio-range ::= <pinctrl-phandle> <gpio-base> '<0 0>' 250 pinctrl-phandle : phandle to pin controller node 251 gpio-base : Base GPIO ID in the GPIO controller 252 pinctrl-base : Base pinctrl pin ID in the pin controller 253 count : The number of GPIOs/pins in this range 254 255The "pin controller node" mentioned above must conform to the bindings 256described in ../pinctrl/pinctrl-bindings.txt. 257 258In case named gpio ranges are used (ranges with both <pinctrl-base> and 259<count> set to 0), the property gpio-ranges-group-names contains one string 260for every single-gpio-range in gpio-ranges: 261 gpiorange-names-list ::= <gpiorange-name> [gpiorange-names-list] 262 gpiorange-name : Name of the pingroup associated to the GPIO range in 263 the respective pin controller. 264 265Elements of gpiorange-names-list corresponding to numeric ranges contain 266the empty string. Elements of gpiorange-names-list corresponding to named 267ranges contain the name of a pin group defined in the respective pin 268controller. The number of pins/GPIOs in the range is the number of pins in 269that pin group. 270 271Previous versions of this binding required all pin controller nodes that 272were referenced by any gpio-ranges property to contain a property named 273#gpio-range-cells with value <3>. This requirement is now deprecated. 274However, that property may still exist in older device trees for 275compatibility reasons, and would still be required even in new device 276trees that need to be compatible with older software. 277 278Example 1: 279 280 qe_pio_e: gpio-controller@1460 { 281 #gpio-cells = <2>; 282 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; 283 reg = <0x1460 0x18>; 284 gpio-controller; 285 gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>; 286 }; 287 288Here, a single GPIO controller has GPIOs 0..9 routed to pin controller 289pinctrl1's pins 20..29, and GPIOs 10..29 routed to pin controller pinctrl2's 290pins 50..69. 291 292Example 2: 293 294 gpio_pio_i: gpio-controller@14b0 { 295 #gpio-cells = <2>; 296 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; 297 reg = <0x1480 0x18>; 298 gpio-controller; 299 gpio-ranges = <&pinctrl1 0 20 10>, 300 <&pinctrl2 10 0 0>, 301 <&pinctrl1 15 0 10>, 302 <&pinctrl2 25 0 0>; 303 gpio-ranges-group-names = "", 304 "foo", 305 "", 306 "bar"; 307 }; 308 309Here, three GPIO ranges are defined wrt. two pin controllers. pinctrl1 GPIO 310ranges are defined using pin numbers whereas the GPIO ranges wrt. pinctrl2 311are named "foo" and "bar". 312