1Specifying GPIO information for devices 2======================================= 3 41) gpios property 5----------------- 6 7GPIO properties should be named "[<name>-]gpios", with <name> being the purpose 8of this GPIO for the device. While a non-existent <name> is considered valid 9for compatibility reasons (resolving to the "gpios" property), it is not allowed 10for new bindings. Also, GPIO properties named "[<name>-]gpio" are valid and old 11bindings use it, but are only supported for compatibility reasons and should not 12be used for newer bindings since it has been deprecated. 13 14GPIO properties can contain one or more GPIO phandles, but only in exceptional 15cases should they contain more than one. If your device uses several GPIOs with 16distinct functions, reference each of them under its own property, giving it a 17meaningful name. The only case where an array of GPIOs is accepted is when 18several GPIOs serve the same function (e.g. a parallel data line). 19 20The exact purpose of each gpios property must be documented in the device tree 21binding of the device. 22 23The following example could be used to describe GPIO pins used as device enable 24and bit-banged data signals: 25 26 gpio1: gpio1 { 27 gpio-controller; 28 #gpio-cells = <2>; 29 }; 30 [...] 31 32 data-gpios = <&gpio1 12 0>, 33 <&gpio1 13 0>, 34 <&gpio1 14 0>, 35 <&gpio1 15 0>; 36 37In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is 38a local offset to the GPIO line and the second cell represent consumer flags, 39such as if the consumer desire the line to be active low (inverted) or open 40drain. This is the recommended practice. 41 42The exact meaning of each specifier cell is controller specific, and must be 43documented in the device tree binding for the device, but it is strongly 44recommended to use the two-cell approach. 45 46Most controllers are specifying a generic flag bitfield in the last cell, so 47for these, use the macros defined in 48include/dt-bindings/gpio/gpio.h whenever possible: 49 50Example of a node using GPIOs: 51 52 node { 53 enable-gpios = <&qe_pio_e 18 GPIO_ACTIVE_HIGH>; 54 }; 55 56GPIO_ACTIVE_HIGH is 0, so in this example gpio-specifier is "18 0" and encodes 57GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller. 58 59Optional standard bitfield specifiers for the last cell: 60 61- Bit 0: 0 means active high, 1 means active low 62- Bit 1: 0 mean push-pull wiring, see: 63 https://en.wikipedia.org/wiki/Push-pull_output 64 1 means single-ended wiring, see: 65 https://en.wikipedia.org/wiki/Single-ended_triode 66- Bit 2: 0 means open-source, 1 means open drain, see: 67 https://en.wikipedia.org/wiki/Open_collector 68- Bit 3: 0 means the output should be maintained during sleep/low-power mode 69 1 means the output state can be lost during sleep/low-power mode 70 711.1) GPIO specifier best practices 72---------------------------------- 73 74A gpio-specifier should contain a flag indicating the GPIO polarity; active- 75high or active-low. If it does, the following best practices should be 76followed: 77 78The gpio-specifier's polarity flag should represent the physical level at the 79GPIO controller that achieves (or represents, for inputs) a logically asserted 80value at the device. The exact definition of logically asserted should be 81defined by the binding for the device. If the board inverts the signal between 82the GPIO controller and the device, then the gpio-specifier will represent the 83opposite physical level than the signal at the device's pin. 84 85When the device's signal polarity is configurable, the binding for the 86device must either: 87 88a) Define a single static polarity for the signal, with the expectation that 89any software using that binding would statically program the device to use 90that signal polarity. 91 92The static choice of polarity may be either: 93 94a1) (Preferred) Dictated by a binding-specific DT property. 95 96or: 97 98a2) Defined statically by the DT binding itself. 99 100In particular, the polarity cannot be derived from the gpio-specifier, since 101that would prevent the DT from separately representing the two orthogonal 102concepts of configurable signal polarity in the device, and possible board- 103level signal inversion. 104 105or: 106 107b) Pick a single option for device signal polarity, and document this choice 108in the binding. The gpio-specifier should represent the polarity of the signal 109(at the GPIO controller) assuming that the device is configured for this 110particular signal polarity choice. If software chooses to program the device 111to generate or receive a signal of the opposite polarity, software will be 112responsible for correctly interpreting (inverting) the GPIO signal at the GPIO 113controller. 114 1152) gpio-controller nodes 116------------------------ 117 118Every GPIO controller node must contain both an empty "gpio-controller" 119property, and a #gpio-cells integer property, which indicates the number of 120cells in a gpio-specifier. 121 122Some system-on-chips (SoCs) use the concept of GPIO banks. A GPIO bank is an 123instance of a hardware IP core on a silicon die, usually exposed to the 124programmer as a coherent range of I/O addresses. Usually each such bank is 125exposed in the device tree as an individual gpio-controller node, reflecting 126the fact that the hardware was synthesized by reusing the same IP block a 127few times over. 128 129Optionally, a GPIO controller may have a "ngpios" property. This property 130indicates the number of in-use slots of available slots for GPIOs. The 131typical example is something like this: the hardware register is 32 bits 132wide, but only 18 of the bits have a physical counterpart. The driver is 133generally written so that all 32 bits can be used, but the IP block is reused 134in a lot of designs, some using all 32 bits, some using 18 and some using 13512. In this case, setting "ngpios = <18>;" informs the driver that only the 136first 18 GPIOs, at local offset 0 .. 17, are in use. 137 138If these GPIOs do not happen to be the first N GPIOs at offset 0...N-1, an 139additional set of tuples is needed to specify which GPIOs are unusable, with 140the gpio-reserved-ranges binding. This property indicates the start and size 141of the GPIOs that can't be used. 142 143Optionally, a GPIO controller may have a "gpio-line-names" property. This is 144an array of strings defining the names of the GPIO lines going out of the 145GPIO controller. This name should be the most meaningful producer name 146for the system, such as a rail name indicating the usage. Package names 147such as pin name are discouraged: such lines have opaque names (since they 148are by definition generic purpose) and such names are usually not very 149helpful. For example "MMC-CD", "Red LED Vdd" and "ethernet reset" are 150reasonable line names as they describe what the line is used for. "GPIO0" 151is not a good name to give to a GPIO line. Placeholders are discouraged: 152rather use the "" (blank string) if the use of the GPIO line is undefined 153in your design. The names are assigned starting from line offset 0 from 154left to right from the passed array. An incomplete array (where the number 155of passed named are less than ngpios) will still be used up until the last 156provided valid line index. 157 158Example: 159 160gpio-controller@00000000 { 161 compatible = "foo"; 162 reg = <0x00000000 0x1000>; 163 gpio-controller; 164 #gpio-cells = <2>; 165 ngpios = <18>; 166 gpio-reserved-ranges = <0 4>, <12 2>; 167 gpio-line-names = "MMC-CD", "MMC-WP", "VDD eth", "RST eth", "LED R", 168 "LED G", "LED B", "Col A", "Col B", "Col C", "Col D", 169 "Row A", "Row B", "Row C", "Row D", "NMI button", 170 "poweroff", "reset"; 171} 172 173The GPIO chip may contain GPIO hog definitions. GPIO hogging is a mechanism 174providing automatic GPIO request and configuration as part of the 175gpio-controller's driver probe function. 176 177Each GPIO hog definition is represented as a child node of the GPIO controller. 178Required properties: 179- gpio-hog: A property specifying that this child node represents a GPIO hog. 180- gpios: Store the GPIO information (id, flags, ...) for each GPIO to 181 affect. Shall contain an integer multiple of the number of cells 182 specified in its parent node (GPIO controller node). 183Only one of the following properties scanned in the order shown below. 184This means that when multiple properties are present they will be searched 185in the order presented below and the first match is taken as the intended 186configuration. 187- input: A property specifying to set the GPIO direction as input. 188- output-low A property specifying to set the GPIO direction as output with 189 the value low. 190- output-high A property specifying to set the GPIO direction as output with 191 the value high. 192 193Optional properties: 194- line-name: The GPIO label name. If not present the node name is used. 195 196Example of two SOC GPIO banks defined as gpio-controller nodes: 197 198 qe_pio_a: gpio-controller@1400 { 199 compatible = "fsl,qe-pario-bank-a", "fsl,qe-pario-bank"; 200 reg = <0x1400 0x18>; 201 gpio-controller; 202 #gpio-cells = <2>; 203 204 line_b { 205 gpio-hog; 206 gpios = <6 0>; 207 output-low; 208 line-name = "foo-bar-gpio"; 209 }; 210 }; 211 212 qe_pio_e: gpio-controller@1460 { 213 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; 214 reg = <0x1460 0x18>; 215 gpio-controller; 216 #gpio-cells = <2>; 217 }; 218 2192.1) gpio- and pin-controller interaction 220----------------------------------------- 221 222Some or all of the GPIOs provided by a GPIO controller may be routed to pins 223on the package via a pin controller. This allows muxing those pins between 224GPIO and other functions. It is a fairly common practice among silicon 225engineers. 226 2272.2) Ordinary (numerical) GPIO ranges 228------------------------------------- 229 230It is useful to represent which GPIOs correspond to which pins on which pin 231controllers. The gpio-ranges property described below represents this with 232a discrete set of ranges mapping pins from the pin controller local number space 233to pins in the GPIO controller local number space. 234 235The format is: <[pin controller phandle], [GPIO controller offset], 236 [pin controller offset], [number of pins]>; 237 238The GPIO controller offset pertains to the GPIO controller node containing the 239range definition. 240 241The pin controller node referenced by the phandle must conform to the bindings 242described in pinctrl/pinctrl-bindings.txt. 243 244Each offset runs from 0 to N. It is perfectly fine to pile any number of 245ranges with just one pin-to-GPIO line mapping if the ranges are concocted, but 246in practice these ranges are often lumped in discrete sets. 247 248Example: 249 250 gpio-ranges = <&foo 0 20 10>, <&bar 10 50 20>; 251 252This means: 253- pins 20..29 on pin controller "foo" is mapped to GPIO line 0..9 and 254- pins 50..69 on pin controller "bar" is mapped to GPIO line 10..29 255 256 257Verbose example: 258 259 qe_pio_e: gpio-controller@1460 { 260 #gpio-cells = <2>; 261 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; 262 reg = <0x1460 0x18>; 263 gpio-controller; 264 gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>; 265 }; 266 267Here, a single GPIO controller has GPIOs 0..9 routed to pin controller 268pinctrl1's pins 20..29, and GPIOs 10..29 routed to pin controller pinctrl2's 269pins 50..69. 270 271 2722.3) GPIO ranges from named pin groups 273-------------------------------------- 274 275It is also possible to use pin groups for gpio ranges when pin groups are the 276easiest and most convenient mapping. 277 278Both both <pinctrl-base> and <count> must set to 0 when using named pin groups 279names. 280 281The property gpio-ranges-group-names must contain exactly one string for each 282range. 283 284Elements of gpio-ranges-group-names must contain the name of a pin group 285defined in the respective pin controller. The number of pins/GPIO lines in the 286range is the number of pins in that pin group. The number of pins of that 287group is defined int the implementation and not in the device tree. 288 289If numerical and named pin groups are mixed, the string corresponding to a 290numerical pin range in gpio-ranges-group-names must be empty. 291 292Example: 293 294 gpio_pio_i: gpio-controller@14b0 { 295 #gpio-cells = <2>; 296 compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank"; 297 reg = <0x1480 0x18>; 298 gpio-controller; 299 gpio-ranges = <&pinctrl1 0 20 10>, 300 <&pinctrl2 10 0 0>, 301 <&pinctrl1 15 0 10>, 302 <&pinctrl2 25 0 0>; 303 gpio-ranges-group-names = "", 304 "foo", 305 "", 306 "bar"; 307 }; 308 309Here, three GPIO ranges are defined referring to two pin controllers. 310 311pinctrl1 GPIO ranges are defined using pin numbers whereas the GPIO ranges 312in pinctrl2 are defined using the pin groups named "foo" and "bar". 313 314Previous versions of this binding required all pin controller nodes that 315were referenced by any gpio-ranges property to contain a property named 316#gpio-range-cells with value <3>. This requirement is now deprecated. 317However, that property may still exist in older device trees for 318compatibility reasons, and would still be required even in new device 319trees that need to be compatible with older software. 320