1a36e9a1cSJohn CrispinLantiq SoC External Bus memory mapped GPIO controller 2a36e9a1cSJohn Crispin 3a36e9a1cSJohn CrispinBy attaching hardware latches to the EBU it is possible to create output 4a36e9a1cSJohn Crispinonly gpios. This driver configures a special memory address, which when 5a36e9a1cSJohn Crispinwritten to outputs 16 bit to the latches. 6a36e9a1cSJohn Crispin 7a36e9a1cSJohn CrispinThe node describing the memory mapped GPIOs needs to be a child of the node 8a36e9a1cSJohn Crispindescribing the "lantiq,localbus". 9a36e9a1cSJohn Crispin 10a36e9a1cSJohn CrispinRequired properties: 11a36e9a1cSJohn Crispin- compatible : Should be "lantiq,gpio-mm-lantiq" 12a36e9a1cSJohn Crispin- reg : Address and length of the register set for the device 13a36e9a1cSJohn Crispin- #gpio-cells : Should be two. The first cell is the pin number and 14a36e9a1cSJohn Crispin the second cell is used to specify optional parameters (currently 15a36e9a1cSJohn Crispin unused). 16a36e9a1cSJohn Crispin- gpio-controller : Marks the device node as a gpio controller. 17a36e9a1cSJohn Crispin 18a36e9a1cSJohn CrispinOptional properties: 19a36e9a1cSJohn Crispin- lantiq,shadow : The default value that we shall assume as already set on the 20a36e9a1cSJohn Crispin shift register cascade. 21a36e9a1cSJohn Crispin 22a36e9a1cSJohn CrispinExample: 23a36e9a1cSJohn Crispin 24a36e9a1cSJohn Crispinlocalbus@0 { 25a36e9a1cSJohn Crispin #address-cells = <2>; 26a36e9a1cSJohn Crispin #size-cells = <1>; 27a36e9a1cSJohn Crispin ranges = <0 0 0x0 0x3ffffff /* addrsel0 */ 28a36e9a1cSJohn Crispin 1 0 0x4000000 0x4000010>; /* addsel1 */ 29a36e9a1cSJohn Crispin compatible = "lantiq,localbus", "simple-bus"; 30a36e9a1cSJohn Crispin 31a36e9a1cSJohn Crispin gpio_mm0: gpio@4000000 { 32a36e9a1cSJohn Crispin compatible = "lantiq,gpio-mm"; 33a36e9a1cSJohn Crispin reg = <1 0x0 0x10>; 34a36e9a1cSJohn Crispin gpio-controller; 35a36e9a1cSJohn Crispin #gpio-cells = <2>; 36a36e9a1cSJohn Crispin lantiq,shadow = <0x77f> 37a36e9a1cSJohn Crispin }; 38a36e9a1cSJohn Crispin} 39