1*d4fd4f01SNobuhiro Iwamatsu# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*d4fd4f01SNobuhiro Iwamatsu%YAML 1.2 3*d4fd4f01SNobuhiro Iwamatsu--- 4*d4fd4f01SNobuhiro Iwamatsu$id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml# 5*d4fd4f01SNobuhiro Iwamatsu$schema: http://devicetree.org/meta-schemas/core.yaml# 6*d4fd4f01SNobuhiro Iwamatsu 7*d4fd4f01SNobuhiro Iwamatsutitle: Xilinx Zynq Ultrascale MPSoC FPGA Manager Device Tree Bindings 8*d4fd4f01SNobuhiro Iwamatsu 9*d4fd4f01SNobuhiro Iwamatsumaintainers: 10*d4fd4f01SNobuhiro Iwamatsu - Nava kishore Manne <navam@xilinx.com> 11*d4fd4f01SNobuhiro Iwamatsu 12*d4fd4f01SNobuhiro Iwamatsudescription: | 13*d4fd4f01SNobuhiro Iwamatsu Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager. 14*d4fd4f01SNobuhiro Iwamatsu The ZynqMP SoC uses the PCAP (Processor Configuration Port) to 15*d4fd4f01SNobuhiro Iwamatsu configure the Programmable Logic (PL). The configuration uses the 16*d4fd4f01SNobuhiro Iwamatsu firmware interface. 17*d4fd4f01SNobuhiro Iwamatsu 18*d4fd4f01SNobuhiro Iwamatsuproperties: 19*d4fd4f01SNobuhiro Iwamatsu compatible: 20*d4fd4f01SNobuhiro Iwamatsu const: xlnx,zynqmp-pcap-fpga 21*d4fd4f01SNobuhiro Iwamatsu 22*d4fd4f01SNobuhiro Iwamatsurequired: 23*d4fd4f01SNobuhiro Iwamatsu - compatible 24*d4fd4f01SNobuhiro Iwamatsu 25*d4fd4f01SNobuhiro IwamatsuadditionalProperties: false 26*d4fd4f01SNobuhiro Iwamatsu 27*d4fd4f01SNobuhiro Iwamatsuexamples: 28*d4fd4f01SNobuhiro Iwamatsu - | 29*d4fd4f01SNobuhiro Iwamatsu firmware { 30*d4fd4f01SNobuhiro Iwamatsu zynqmp_firmware: zynqmp-firmware { 31*d4fd4f01SNobuhiro Iwamatsu zynqmp_pcap: pcap { 32*d4fd4f01SNobuhiro Iwamatsu compatible = "xlnx,zynqmp-pcap-fpga"; 33*d4fd4f01SNobuhiro Iwamatsu }; 34*d4fd4f01SNobuhiro Iwamatsu }; 35*d4fd4f01SNobuhiro Iwamatsu }; 36*d4fd4f01SNobuhiro Iwamatsu... 37