1*b7eb6da9SIvan Bornyakov# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*b7eb6da9SIvan Bornyakov%YAML 1.2 3*b7eb6da9SIvan Bornyakov--- 4*b7eb6da9SIvan Bornyakov$id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml# 5*b7eb6da9SIvan Bornyakov$schema: http://devicetree.org/meta-schemas/core.yaml# 6*b7eb6da9SIvan Bornyakov 7*b7eb6da9SIvan Bornyakovtitle: Microchip Polarfire FPGA manager. 8*b7eb6da9SIvan Bornyakov 9*b7eb6da9SIvan Bornyakovmaintainers: 10*b7eb6da9SIvan Bornyakov - Ivan Bornyakov <i.bornyakov@metrotek.ru> 11*b7eb6da9SIvan Bornyakov 12*b7eb6da9SIvan Bornyakovdescription: 13*b7eb6da9SIvan Bornyakov Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to 14*b7eb6da9SIvan Bornyakov load the bitstream in .dat format. 15*b7eb6da9SIvan Bornyakov 16*b7eb6da9SIvan Bornyakovproperties: 17*b7eb6da9SIvan Bornyakov compatible: 18*b7eb6da9SIvan Bornyakov enum: 19*b7eb6da9SIvan Bornyakov - microchip,mpf-spi-fpga-mgr 20*b7eb6da9SIvan Bornyakov 21*b7eb6da9SIvan Bornyakov reg: 22*b7eb6da9SIvan Bornyakov description: SPI chip select 23*b7eb6da9SIvan Bornyakov maxItems: 1 24*b7eb6da9SIvan Bornyakov 25*b7eb6da9SIvan Bornyakov spi-max-frequency: true 26*b7eb6da9SIvan Bornyakov 27*b7eb6da9SIvan Bornyakovrequired: 28*b7eb6da9SIvan Bornyakov - compatible 29*b7eb6da9SIvan Bornyakov - reg 30*b7eb6da9SIvan Bornyakov 31*b7eb6da9SIvan BornyakovadditionalProperties: false 32*b7eb6da9SIvan Bornyakov 33*b7eb6da9SIvan Bornyakovexamples: 34*b7eb6da9SIvan Bornyakov - | 35*b7eb6da9SIvan Bornyakov spi { 36*b7eb6da9SIvan Bornyakov #address-cells = <1>; 37*b7eb6da9SIvan Bornyakov #size-cells = <0>; 38*b7eb6da9SIvan Bornyakov 39*b7eb6da9SIvan Bornyakov fpga_mgr@0 { 40*b7eb6da9SIvan Bornyakov compatible = "microchip,mpf-spi-fpga-mgr"; 41*b7eb6da9SIvan Bornyakov spi-max-frequency = <20000000>; 42*b7eb6da9SIvan Bornyakov reg = <0>; 43*b7eb6da9SIvan Bornyakov }; 44*b7eb6da9SIvan Bornyakov }; 45