1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra Boot and Power Management Processor (BPMP)
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12
13description: |
14  The BPMP is a specific processor in Tegra chip, which is designed for
15  booting process handling and offloading the power management, clock
16  management, and reset control tasks from the CPU. The binding document
17  defines the resources that would be used by the BPMP firmware driver,
18  which can create the interprocessor communication (IPC) between the
19  CPU and BPMP.
20
21  This node is a mailbox consumer. See the following files for details
22  of the mailbox subsystem, and the specifiers implemented by the
23  relevant provider(s):
24
25    - .../mailbox/mailbox.txt
26    - .../mailbox/nvidia,tegra186-hsp.yaml
27
28  This node is a clock, power domain, and reset provider. See the
29  following files for general documentation of those features, and the
30  specifiers implemented by this node:
31
32    - .../clock/clock-bindings.txt
33    - <dt-bindings/clock/tegra186-clock.h>
34    - ../power/power-domain.yaml
35    - <dt-bindings/power/tegra186-powergate.h>
36    - .../reset/reset.txt
37    - <dt-bindings/reset/tegra186-reset.h>
38
39  The BPMP implements some services which must be represented by
40  separate nodes. For example, it can provide access to certain I2C
41  controllers, and the I2C bindings represent each I2C controller as a
42  device tree node. Such nodes should be nested directly inside the main
43  BPMP node.
44
45  Software can determine whether a child node of the BPMP node
46  represents a device by checking for a compatible property. Any node
47  with a compatible property represents a device that can be
48  instantiated. Nodes without a compatible property may be used to
49  provide configuration information regarding the BPMP itself, although
50  no such configuration nodes are currently defined by this binding.
51
52  The BPMP firmware defines no single global name-/numbering-space for
53  such services. Put another way, the numbering scheme for I2C buses is
54  distinct from the numbering scheme for any other service the BPMP may
55  provide (e.g. a future hypothetical SPI bus service). As such, child
56  device nodes will have no reg property, and the BPMP node will have no
57  "#address-cells" or "#size-cells" property.
58
59  The shared memory area for the IPC TX and RX between CPU and BPMP are
60  predefined and work on top of sysram, which is an SRAM inside the
61  chip. See ".../sram/sram.yaml" for the bindings.
62
63properties:
64  compatible:
65    oneOf:
66      - items:
67          - enum:
68              - nvidia,tegra194-bpmp
69              - nvidia,tegra234-bpmp
70          - const: nvidia,tegra186-bpmp
71      - const: nvidia,tegra186-bpmp
72
73  mboxes:
74    description: A phandle and channel specifier for the mailbox used to
75      communicate with the BPMP.
76    maxItems: 1
77
78  shmem:
79    description: List of the phandle to the TX and RX shared memory area
80      that the IPC between CPU and BPMP is based on.
81    minItems: 2
82    maxItems: 2
83
84  "#clock-cells":
85    const: 1
86
87  "#power-domain-cells":
88    const: 1
89
90  "#reset-cells":
91    const: 1
92
93  interconnects:
94    items:
95      - description: memory read client
96      - description: memory write client
97      - description: DMA read client
98      - description: DMA write client
99
100  interconnect-names:
101    items:
102      - const: read
103      - const: write
104      - const: dma-mem # dma-read
105      - const: dma-write
106
107  iommus:
108    maxItems: 1
109
110  i2c:
111    type: object
112
113  thermal:
114    type: object
115
116additionalProperties: false
117
118required:
119  - compatible
120  - mboxes
121  - shmem
122  - "#clock-cells"
123  - "#power-domain-cells"
124  - "#reset-cells"
125
126examples:
127  - |
128    #include <dt-bindings/interrupt-controller/arm-gic.h>
129    #include <dt-bindings/mailbox/tegra186-hsp.h>
130    #include <dt-bindings/memory/tegra186-mc.h>
131
132    hsp_top0: hsp@3c00000 {
133        compatible = "nvidia,tegra186-hsp";
134        reg = <0x03c00000 0xa0000>;
135        interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
136        interrupt-names = "doorbell";
137        #mbox-cells = <2>;
138    };
139
140    sram@30000000 {
141        compatible = "nvidia,tegra186-sysram", "mmio-sram";
142        reg = <0x30000000 0x50000>;
143        #address-cells = <1>;
144        #size-cells = <1>;
145        ranges = <0x0 0x30000000 0x50000>;
146
147        cpu_bpmp_tx: sram@4e000 {
148            reg = <0x4e000 0x1000>;
149            label = "cpu-bpmp-tx";
150            pool;
151        };
152
153        cpu_bpmp_rx: sram@4f000 {
154            reg = <0x4f000 0x1000>;
155            label = "cpu-bpmp-rx";
156            pool;
157        };
158    };
159
160    bpmp {
161        compatible = "nvidia,tegra186-bpmp";
162        interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>,
163                        <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>,
164                        <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>,
165                        <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>;
166        interconnect-names = "read", "write", "dma-mem", "dma-write";
167        iommus = <&smmu TEGRA186_SID_BPMP>;
168        mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
169                            TEGRA_HSP_DB_MASTER_BPMP>;
170        shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
171        #clock-cells = <1>;
172        #power-domain-cells = <1>;
173        #reset-cells = <1>;
174
175        i2c {
176            compatible = "nvidia,tegra186-bpmp-i2c";
177            nvidia,bpmp-bus-id = <5>;
178            #address-cells = <1>;
179            #size-cells = <0>;
180        };
181
182        thermal {
183            compatible = "nvidia,tegra186-bpmp-thermal";
184            #thermal-sensor-cells = <1>;
185        };
186    };
187