1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP i.MX System Controller Firmware (SCFW)
8
9maintainers:
10  - Dong Aisheng <aisheng.dong@nxp.com>
11
12description:
13  The System Controller Firmware (SCFW) is a low-level system function
14  which runs on a dedicated Cortex-M core to provide power, clock, and
15  resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
16  (QM, QP), and i.MX8QX (QXP, DX).
17  The AP communicates with the SC using a multi-ported MU module found
18  in the LSIO subsystem. The current definition of this MU module provides
19  5 remote AP connections to the SC to support up to 5 execution environments
20  (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
21  with the LSIO DSC IP bus. The SC firmware will communicate with this MU
22  using the MSI bus.
23
24properties:
25  compatible:
26    const: fsl,imx-scu
27
28  clock-controller:
29    description:
30      Clock controller node that provides the clocks controlled by the SCU
31    $ref: /schemas/clock/fsl,scu-clk.yaml
32
33  gpio:
34    description:
35      Control the GPIO PINs on SCU domain over the firmware APIs
36    $ref: /schemas/gpio/fsl,imx8qxp-sc-gpio.yaml
37
38  ocotp:
39    description:
40      OCOTP controller node provided by the SCU
41    $ref: /schemas/nvmem/fsl,scu-ocotp.yaml
42
43  keys:
44    description:
45      Keys provided by the SCU
46    $ref: /schemas/input/fsl,scu-key.yaml
47
48  mboxes:
49    description:
50      A list of phandles of TX MU channels followed by a list of phandles of
51      RX MU channels. The list may include at the end one more optional MU
52      channel for general interrupt. The number of expected tx and rx
53      channels is 1 TX and 1 RX channels if MU instance is "fsl,imx8-mu-scu"
54      compatible, 4 TX and 4 RX channels otherwise. All MU channels must be
55      within the same MU instance. Cross instances are not allowed. The MU
56      instance can only be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users
57      need to ensure that one is used that does not conflict with other
58      execution environments such as ATF.
59    oneOf:
60      - items:
61          - description: TX0 MU channel
62          - description: RX0 MU channel
63      - items:
64          - description: TX0 MU channel
65          - description: RX0 MU channel
66          - description: optional MU channel for general interrupt
67      - items:
68          - description: TX0 MU channel
69          - description: TX1 MU channel
70          - description: TX2 MU channel
71          - description: TX3 MU channel
72          - description: RX0 MU channel
73          - description: RX1 MU channel
74          - description: RX2 MU channel
75          - description: RX3 MU channel
76      - items:
77          - description: TX0 MU channel
78          - description: TX1 MU channel
79          - description: TX2 MU channel
80          - description: TX3 MU channel
81          - description: RX0 MU channel
82          - description: RX1 MU channel
83          - description: RX2 MU channel
84          - description: RX3 MU channel
85          - description: optional MU channel for general interrupt
86
87  mbox-names:
88    oneOf:
89      - items:
90          - const: tx0
91          - const: rx0
92      - items:
93          - const: tx0
94          - const: rx0
95          - const: gip3
96      - items:
97          - const: tx0
98          - const: tx1
99          - const: tx2
100          - const: tx3
101          - const: rx0
102          - const: rx1
103          - const: rx2
104          - const: rx3
105      - items:
106          - const: tx0
107          - const: tx1
108          - const: tx2
109          - const: tx3
110          - const: rx0
111          - const: rx1
112          - const: rx2
113          - const: rx3
114          - const: gip3
115
116  pinctrl:
117    description:
118      Pin controller provided by the SCU
119    $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml
120
121  power-controller:
122    description:
123      Power domains controller node that provides the power domains
124      controlled by the SCU
125    $ref: /schemas/power/fsl,scu-pd.yaml
126
127  rtc:
128    description:
129      RTC controller provided by the SCU
130    $ref: /schemas/rtc/fsl,scu-rtc.yaml
131
132  thermal-sensor:
133    description:
134      Thermal sensor provided by the SCU
135    $ref: /schemas/thermal/fsl,scu-thermal.yaml
136
137  watchdog:
138    description:
139      Watchdog controller provided by the SCU
140    $ref: /schemas/watchdog/fsl,scu-wdt.yaml
141
142required:
143  - compatible
144  - mbox-names
145  - mboxes
146
147additionalProperties: false
148
149examples:
150  - |
151    #include <dt-bindings/firmware/imx/rsrc.h>
152    #include <dt-bindings/input/input.h>
153    #include <dt-bindings/pinctrl/pads-imx8qxp.h>
154
155    firmware {
156        system-controller {
157            compatible = "fsl,imx-scu";
158            mbox-names = "tx0", "tx1", "tx2", "tx3",
159                         "rx0", "rx1", "rx2", "rx3",
160                         "gip3";
161            mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3
162                      &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3
163                      &lsio_mu1 3 3>;
164
165            clock-controller {
166                compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
167                #clock-cells = <2>;
168            };
169
170            pinctrl {
171                compatible = "fsl,imx8qxp-iomuxc";
172
173                pinctrl_lpuart0: lpuart0grp {
174                    fsl,pins = <
175                        IMX8QXP_UART0_RX_ADMA_UART0_RX   0x06000020
176                        IMX8QXP_UART0_TX_ADMA_UART0_TX   0x06000020
177                    >;
178                };
179            };
180
181            ocotp {
182                compatible = "fsl,imx8qxp-scu-ocotp";
183                #address-cells = <1>;
184                #size-cells = <1>;
185
186                fec_mac0: mac@2c4 {
187                    reg = <0x2c4 6>;
188                };
189            };
190
191            power-controller {
192                compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
193                #power-domain-cells = <1>;
194            };
195
196            rtc {
197                compatible = "fsl,imx8qxp-sc-rtc";
198            };
199
200            keys {
201                compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
202                linux,keycodes = <KEY_POWER>;
203            };
204
205            watchdog {
206                compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
207                timeout-sec = <60>;
208            };
209
210            thermal-sensor {
211                compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
212                #thermal-sensor-cells = <1>;
213            };
214        };
215    };
216