1Aspeed AST2500 SoC EDAC node
2
3The Aspeed AST2500 SoC supports DDR3 and DDR4 memory with and without ECC (error
4correction check).
5
6The memory controller supports SECDED (single bit error correction, double bit
7error detection) and single bit error auto scrubbing by reserving 8 bits for
8every 64 bit word (effectively reducing available memory to 8/9).
9
10Note, the bootloader must configure ECC mode in the memory controller.
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12
13Required properties:
14- compatible: should be "aspeed,ast2500-sdram-edac"
15- reg:        sdram controller register set should be <0x1e6e0000 0x174>
16- interrupts: should be AVIC interrupt #0
17
18
19Example:
20
21	edac: sdram@1e6e0000 {
22		compatible = "aspeed,ast2500-sdram-edac";
23		reg = <0x1e6e0000 0x174>;
24		interrupts = <0>;
25	};
26