1* APM X-Gene SoC EDAC node
2
3EDAC node is defined to describe on-chip error detection and correction.
4The follow error types are supported:
5
6  memory controller	- Memory controller
7  PMD (L1/L2)		- Processor module unit (PMD) L1/L2 cache
8  L3			- L3 cache controller
9  SoC			- SoC IP's such as Ethernet, SATA, and etc
10
11The following section describes the EDAC DT node binding.
12
13Required properties:
14- compatible		: Shall be "apm,xgene-edac".
15- regmap-csw		: Regmap of the CPU switch fabric (CSW) resource.
16- regmap-mcba		: Regmap of the MCB-A (memory bridge) resource.
17- regmap-mcbb		: Regmap of the MCB-B (memory bridge) resource.
18- regmap-efuse		: Regmap of the PMD efuse resource.
19- reg			: First resource shall be the CPU bus (PCP) resource.
20- interrupts            : Interrupt-specifier for MCU, PMD, L3, or SoC error
21			  IRQ(s).
22
23Required properties for memory controller subnode:
24- compatible		: Shall be "apm,xgene-edac-mc".
25- reg			: First resource shall be the memory controller unit
26                          (MCU) resource.
27- memory-controller	: Instance number of the memory controller.
28
29Required properties for PMD subnode:
30- compatible		: Shall be "apm,xgene-edac-pmd" or
31                          "apm,xgene-edac-pmd-v2".
32- reg			: First resource shall be the PMD resource.
33- pmd-controller	: Instance number of the PMD controller.
34
35Required properties for L3 subnode:
36- compatible		: Shall be "apm,xgene-edac-l3" or
37                          "apm,xgene-edac-l3-v2".
38- reg			: First resource shall be the L3 EDAC resource.
39
40Required properties for SoC subnode:
41- compatible		: Shall be "apm,xgene-edac-soc-v1" for revision 1 or
42                          "apm,xgene-edac-l3-soc" for general value reporting
43                          only.
44- reg			: First resource shall be the SoC EDAC resource.
45
46Example:
47	csw: csw@7e200000 {
48		compatible = "apm,xgene-csw", "syscon";
49		reg = <0x0 0x7e200000 0x0 0x1000>;
50	};
51
52	mcba: mcba@7e700000 {
53		compatible = "apm,xgene-mcb", "syscon";
54		reg = <0x0 0x7e700000 0x0 0x1000>;
55	};
56
57	mcbb: mcbb@7e720000 {
58		compatible = "apm,xgene-mcb", "syscon";
59		reg = <0x0 0x7e720000 0x0 0x1000>;
60	};
61
62	efuse: efuse@1054a000 {
63		compatible = "apm,xgene-efuse", "syscon";
64		reg = <0x0 0x1054a000 0x0 0x20>;
65	};
66
67	edac@78800000 {
68		compatible = "apm,xgene-edac";
69		#address-cells = <2>;
70		#size-cells = <2>;
71		ranges;
72		regmap-csw = <&csw>;
73		regmap-mcba = <&mcba>;
74		regmap-mcbb = <&mcbb>;
75		regmap-efuse = <&efuse>;
76		reg = <0x0 0x78800000 0x0 0x100>;
77		interrupts = <0x0 0x20 0x4>,
78			     <0x0 0x21 0x4>,
79			     <0x0 0x27 0x4>;
80
81		edacmc@7e800000 {
82			compatible = "apm,xgene-edac-mc";
83			reg = <0x0 0x7e800000 0x0 0x1000>;
84			memory-controller = <0>;
85		};
86
87		edacpmd@7c000000 {
88			compatible = "apm,xgene-edac-pmd";
89			reg = <0x0 0x7c000000 0x0 0x200000>;
90			pmd-controller = <0>;
91		};
92
93		edacl3@7e600000 {
94			compatible = "apm,xgene-edac-l3";
95			reg = <0x0 0x7e600000 0x0 0x1000>;
96		};
97
98		edacsoc@7e930000 {
99			compatible = "apm,xgene-edac-soc-v1";
100			reg = <0x0 0x7e930000 0x0 0x1000>;
101		};
102	};
103