17db2f2dfSDaniel Baluta# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
27db2f2dfSDaniel Baluta%YAML 1.2
37db2f2dfSDaniel Baluta---
47db2f2dfSDaniel Baluta$id: http://devicetree.org/schemas/dsp/fsl,dsp.yaml#
57db2f2dfSDaniel Baluta$schema: http://devicetree.org/meta-schemas/core.yaml#
67db2f2dfSDaniel Baluta
77db2f2dfSDaniel Balutatitle: NXP i.MX8 DSP core
87db2f2dfSDaniel Baluta
97db2f2dfSDaniel Balutamaintainers:
107db2f2dfSDaniel Baluta  - Daniel Baluta <daniel.baluta@nxp.com>
11*b55553fdSShengjiu Wang  - Shengjiu Wang <shengjiu.wang@nxp.com>
127db2f2dfSDaniel Baluta
137db2f2dfSDaniel Balutadescription: |
147db2f2dfSDaniel Baluta  Some boards from i.MX8 family contain a DSP core used for
157db2f2dfSDaniel Baluta  advanced pre- and post- audio processing.
167db2f2dfSDaniel Baluta
177db2f2dfSDaniel Balutaproperties:
187db2f2dfSDaniel Baluta  compatible:
197db2f2dfSDaniel Baluta    enum:
207db2f2dfSDaniel Baluta      - fsl,imx8qxp-dsp
2135a0f242SDaniel Baluta      - fsl,imx8qm-dsp
2235a0f242SDaniel Baluta      - fsl,imx8mp-dsp
23*b55553fdSShengjiu Wang      - fsl,imx8qxp-hifi4
24*b55553fdSShengjiu Wang      - fsl,imx8qm-hifi4
25*b55553fdSShengjiu Wang      - fsl,imx8mp-hifi4
26*b55553fdSShengjiu Wang      - fsl,imx8ulp-hifi4
277db2f2dfSDaniel Baluta
287db2f2dfSDaniel Baluta  reg:
290499220dSRob Herring    maxItems: 1
307db2f2dfSDaniel Baluta
317db2f2dfSDaniel Baluta  clocks:
327db2f2dfSDaniel Baluta    items:
337db2f2dfSDaniel Baluta      - description: ipg clock
347db2f2dfSDaniel Baluta      - description: ocram clock
357db2f2dfSDaniel Baluta      - description: core clock
36*b55553fdSShengjiu Wang      - description: debug interface clock
37*b55553fdSShengjiu Wang      - description: message unit clock
38*b55553fdSShengjiu Wang    minItems: 3
397db2f2dfSDaniel Baluta
407db2f2dfSDaniel Baluta  clock-names:
417db2f2dfSDaniel Baluta    items:
427db2f2dfSDaniel Baluta      - const: ipg
437db2f2dfSDaniel Baluta      - const: ocram
447db2f2dfSDaniel Baluta      - const: core
45*b55553fdSShengjiu Wang      - const: debug
46*b55553fdSShengjiu Wang      - const: mu
47*b55553fdSShengjiu Wang    minItems: 3
487db2f2dfSDaniel Baluta
497db2f2dfSDaniel Baluta  power-domains:
507db2f2dfSDaniel Baluta    description:
517db2f2dfSDaniel Baluta      List of phandle and PM domain specifier as documented in
527db2f2dfSDaniel Baluta      Documentation/devicetree/bindings/power/power_domain.txt
53*b55553fdSShengjiu Wang    minItems: 1
547db2f2dfSDaniel Baluta    maxItems: 4
557db2f2dfSDaniel Baluta
567db2f2dfSDaniel Baluta  mboxes:
577db2f2dfSDaniel Baluta    description:
587db2f2dfSDaniel Baluta      List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB
59*b55553fdSShengjiu Wang      or - 1 channel for TX, 1 channel for RX, 1 channel for RXDB
607db2f2dfSDaniel Baluta      (see mailbox/fsl,mu.txt)
61*b55553fdSShengjiu Wang    minItems: 3
627db2f2dfSDaniel Baluta    maxItems: 4
637db2f2dfSDaniel Baluta
647db2f2dfSDaniel Baluta  mbox-names:
65*b55553fdSShengjiu Wang    minItems: 3
66*b55553fdSShengjiu Wang    maxItems: 4
677db2f2dfSDaniel Baluta
687db2f2dfSDaniel Baluta  memory-region:
697db2f2dfSDaniel Baluta    description:
707db2f2dfSDaniel Baluta      phandle to a node describing reserved memory (System RAM memory)
717db2f2dfSDaniel Baluta      used by DSP (see bindings/reserved-memory/reserved-memory.txt)
72*b55553fdSShengjiu Wang    minItems: 1
73*b55553fdSShengjiu Wang    maxItems: 4
74*b55553fdSShengjiu Wang
75*b55553fdSShengjiu Wang  firmware-name:
76*b55553fdSShengjiu Wang    description: |
77*b55553fdSShengjiu Wang      Default name of the firmware to load to the remote processor.
78*b55553fdSShengjiu Wang
79*b55553fdSShengjiu Wang  fsl,dsp-ctrl:
80*b55553fdSShengjiu Wang    $ref: /schemas/types.yaml#/definitions/phandle
81*b55553fdSShengjiu Wang    description:
82*b55553fdSShengjiu Wang      Phandle to syscon block which provide access for processor enablement
837db2f2dfSDaniel Baluta
847db2f2dfSDaniel Balutarequired:
857db2f2dfSDaniel Baluta  - compatible
867db2f2dfSDaniel Baluta  - reg
877db2f2dfSDaniel Baluta  - clocks
887db2f2dfSDaniel Baluta  - clock-names
897db2f2dfSDaniel Baluta  - power-domains
907db2f2dfSDaniel Baluta  - mboxes
917db2f2dfSDaniel Baluta  - mbox-names
927db2f2dfSDaniel Baluta  - memory-region
937db2f2dfSDaniel Baluta
94*b55553fdSShengjiu WangallOf:
95*b55553fdSShengjiu Wang  - if:
96*b55553fdSShengjiu Wang      properties:
97*b55553fdSShengjiu Wang        compatible:
98*b55553fdSShengjiu Wang          contains:
99*b55553fdSShengjiu Wang            enum:
100*b55553fdSShengjiu Wang              - fsl,imx8qxp-dsp
101*b55553fdSShengjiu Wang              - fsl,imx8qm-dsp
102*b55553fdSShengjiu Wang              - fsl,imx8qxp-hifi4
103*b55553fdSShengjiu Wang              - fsl,imx8qm-hifi4
104*b55553fdSShengjiu Wang    then:
105*b55553fdSShengjiu Wang      properties:
106*b55553fdSShengjiu Wang        power-domains:
107*b55553fdSShengjiu Wang          minItems: 4
108*b55553fdSShengjiu Wang    else:
109*b55553fdSShengjiu Wang      properties:
110*b55553fdSShengjiu Wang        power-domains:
111*b55553fdSShengjiu Wang          maxItems: 1
112*b55553fdSShengjiu Wang
113*b55553fdSShengjiu Wang  - if:
114*b55553fdSShengjiu Wang      properties:
115*b55553fdSShengjiu Wang        compatible:
116*b55553fdSShengjiu Wang          contains:
117*b55553fdSShengjiu Wang            enum:
118*b55553fdSShengjiu Wang              - fsl,imx8qxp-hifi4
119*b55553fdSShengjiu Wang              - fsl,imx8qm-hifi4
120*b55553fdSShengjiu Wang              - fsl,imx8mp-hifi4
121*b55553fdSShengjiu Wang              - fsl,imx8ulp-hifi4
122*b55553fdSShengjiu Wang    then:
123*b55553fdSShengjiu Wang      properties:
124*b55553fdSShengjiu Wang        memory-region:
125*b55553fdSShengjiu Wang          minItems: 4
126*b55553fdSShengjiu Wang        mboxes:
127*b55553fdSShengjiu Wang          maxItems: 3
128*b55553fdSShengjiu Wang        mbox-names:
129*b55553fdSShengjiu Wang          items:
130*b55553fdSShengjiu Wang            - const: tx
131*b55553fdSShengjiu Wang            - const: rx
132*b55553fdSShengjiu Wang            - const: rxdb
133*b55553fdSShengjiu Wang    else:
134*b55553fdSShengjiu Wang      properties:
135*b55553fdSShengjiu Wang        memory-region:
136*b55553fdSShengjiu Wang          maxItems: 1
137*b55553fdSShengjiu Wang        mboxes:
138*b55553fdSShengjiu Wang          minItems: 4
139*b55553fdSShengjiu Wang        mbox-names:
140*b55553fdSShengjiu Wang          items:
141*b55553fdSShengjiu Wang            - const: txdb0
142*b55553fdSShengjiu Wang            - const: txdb1
143*b55553fdSShengjiu Wang            - const: rxdb0
144*b55553fdSShengjiu Wang            - const: rxdb1
145*b55553fdSShengjiu Wang
1467f464532SRob HerringadditionalProperties: false
1477f464532SRob Herring
1487db2f2dfSDaniel Balutaexamples:
1497db2f2dfSDaniel Baluta  - |
1507db2f2dfSDaniel Baluta    #include <dt-bindings/firmware/imx/rsrc.h>
1517db2f2dfSDaniel Baluta    #include <dt-bindings/clock/imx8-clock.h>
1527db2f2dfSDaniel Baluta    dsp@596e8000 {
1537db2f2dfSDaniel Baluta        compatible = "fsl,imx8qxp-dsp";
1547db2f2dfSDaniel Baluta        reg = <0x596e8000 0x88000>;
1557db2f2dfSDaniel Baluta        clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
1567db2f2dfSDaniel Baluta                 <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
1577db2f2dfSDaniel Baluta                 <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
1587db2f2dfSDaniel Baluta        clock-names = "ipg", "ocram", "core";
1597db2f2dfSDaniel Baluta        power-domains = <&pd IMX_SC_R_MU_13A>,
1607db2f2dfSDaniel Baluta                        <&pd IMX_SC_R_MU_13B>,
1617db2f2dfSDaniel Baluta                        <&pd IMX_SC_R_DSP>,
1627db2f2dfSDaniel Baluta                        <&pd IMX_SC_R_DSP_RAM>;
1637db2f2dfSDaniel Baluta        mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
1647db2f2dfSDaniel Baluta        mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
165e2973352SMaxime Ripard        memory-region = <&dsp_reserved>;
1667db2f2dfSDaniel Baluta    };
167*b55553fdSShengjiu Wang  - |
168*b55553fdSShengjiu Wang    #include <dt-bindings/clock/imx8mp-clock.h>
169*b55553fdSShengjiu Wang    dsp_reserved: dsp@92400000 {
170*b55553fdSShengjiu Wang      reg = <0x92400000 0x1000000>;
171*b55553fdSShengjiu Wang      no-map;
172*b55553fdSShengjiu Wang    };
173*b55553fdSShengjiu Wang    dsp_vdev0vring0: vdev0vring0@942f0000 {
174*b55553fdSShengjiu Wang      reg = <0x942f0000 0x8000>;
175*b55553fdSShengjiu Wang      no-map;
176*b55553fdSShengjiu Wang    };
177*b55553fdSShengjiu Wang    dsp_vdev0vring1: vdev0vring1@942f8000 {
178*b55553fdSShengjiu Wang      reg = <0x942f8000 0x8000>;
179*b55553fdSShengjiu Wang      no-map;
180*b55553fdSShengjiu Wang    };
181*b55553fdSShengjiu Wang    dsp_vdev0buffer: vdev0buffer@94300000 {
182*b55553fdSShengjiu Wang      compatible = "shared-dma-pool";
183*b55553fdSShengjiu Wang      reg = <0x94300000 0x100000>;
184*b55553fdSShengjiu Wang      no-map;
185*b55553fdSShengjiu Wang    };
186*b55553fdSShengjiu Wang
187*b55553fdSShengjiu Wang    dsp: dsp@3b6e8000 {
188*b55553fdSShengjiu Wang      compatible = "fsl,imx8mp-hifi4";
189*b55553fdSShengjiu Wang      reg = <0x3b6e8000 0x88000>;
190*b55553fdSShengjiu Wang      clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
191*b55553fdSShengjiu Wang               <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>,
192*b55553fdSShengjiu Wang               <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>,
193*b55553fdSShengjiu Wang               <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>;
194*b55553fdSShengjiu Wang      clock-names = "ipg", "ocram", "core", "debug";
195*b55553fdSShengjiu Wang      firmware-name = "imx/dsp/hifi4.bin";
196*b55553fdSShengjiu Wang      power-domains = <&audiomix_pd>;
197*b55553fdSShengjiu Wang      mbox-names = "tx", "rx", "rxdb";
198*b55553fdSShengjiu Wang      mboxes = <&mu2 0 0>,
199*b55553fdSShengjiu Wang               <&mu2 1 0>,
200*b55553fdSShengjiu Wang               <&mu2 3 0>;
201*b55553fdSShengjiu Wang      memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
202*b55553fdSShengjiu Wang                      <&dsp_vdev0vring1>, <&dsp_reserved>;
203*b55553fdSShengjiu Wang      fsl,dsp-ctrl = <&audio_blk_ctrl>;
204*b55553fdSShengjiu Wang    };
205