1Xilinx AXI VDMA engine, it does transfers between memory and video devices. 2It can be configured to have one channel or two channels. If configured 3as two channels, one is to transmit to the video device and another is 4to receive from the video device. 5 6Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream 7target devices. It can be configured to have one channel or two channels. 8If configured as two channels, one is to transmit to the device and another 9is to receive from the device. 10 11Xilinx AXI CDMA engine, it does transfers between memory-mapped source 12address and a memory-mapped destination address. 13 14Xilinx AXI MCDMA engine, it does transfer between memory and AXI4 stream 15target devices. It can be configured to have up to 16 independent transmit 16and receive channels. 17 18Required properties: 19- compatible: Should be one of- 20 "xlnx,axi-vdma-1.00.a" 21 "xlnx,axi-dma-1.00.a" 22 "xlnx,axi-cdma-1.00.a" 23 "xlnx,axi-mcdma-1.00.a" 24- #dma-cells: Should be <1>, see "dmas" property below 25- reg: Should contain VDMA registers location and length. 26- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits). 27- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>. 28- dma-channel child node: Should have at least one channel and can have up to 29 two channels per device. This node specifies the properties of each 30 DMA channel (see child node properties below). 31- clocks: Input clock specifier. Refer to common clock bindings. 32- clock-names: List of input clocks 33 For VDMA: 34 Required elements: "s_axi_lite_aclk" 35 Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk", 36 "m_axis_mm2s_aclk", "s_axis_s2mm_aclk" 37 For CDMA: 38 Required elements: "s_axi_lite_aclk", "m_axi_aclk" 39 For AXIDMA and MCDMA: 40 Required elements: "s_axi_lite_aclk" 41 Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", 42 "m_axi_sg_aclk" 43 44Required properties for VDMA: 45- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. 46 47Optional properties for AXI DMA and MCDMA: 48- xlnx,sg-length-width: Should be set to the width in bits of the length 49 register as configured in h/w. Takes values {8...26}. If the property 50 is missing or invalid then the default value 23 is used. This is the 51 maximum value that is supported by all IP versions. 52 53Optional properties for AXI DMA: 54- xlnx,axistream-connected: Tells whether DMA is connected to AXI stream IP. 55 56Optional properties for VDMA: 57- xlnx,flush-fsync: Tells which channel to Flush on Frame sync. 58 It takes following values: 59 {1}, flush both channels 60 {2}, flush mm2s channel 61 {3}, flush s2mm channel 62 63Required child node properties: 64- compatible: 65 For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or 66 "xlnx,axi-vdma-s2mm-channel". 67 For CDMA: It should be "xlnx,axi-cdma-channel". 68 For AXIDMA and MCDMA: It should be either "xlnx,axi-dma-mm2s-channel" 69 or "xlnx,axi-dma-s2mm-channel". 70- interrupts: Should contain per channel VDMA interrupts. 71- xlnx,datawidth: Should contain the stream data width, take values 72 {32,64...1024}. 73 74Optional child node properties: 75- xlnx,include-dre: Tells hardware is configured for Data 76 Realignment Engine. 77Optional child node properties for VDMA: 78- xlnx,genlock-mode: Tells Genlock synchronization is 79 enabled/disabled in hardware. 80- xlnx,enable-vert-flip: Tells vertical flip is 81 enabled/disabled in hardware(S2MM path). 82Optional child node properties for MCDMA: 83- dma-channels: Number of dma channels in child node. 84 85Example: 86++++++++ 87 88axi_vdma_0: axivdma@40030000 { 89 compatible = "xlnx,axi-vdma-1.00.a"; 90 #dma_cells = <1>; 91 reg = < 0x40030000 0x10000 >; 92 dma-ranges = <0x00000000 0x00000000 0x40000000>; 93 xlnx,num-fstores = <0x8>; 94 xlnx,flush-fsync = <0x1>; 95 xlnx,addrwidth = <0x20>; 96 clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>; 97 clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", 98 "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"; 99 dma-channel@40030000 { 100 compatible = "xlnx,axi-vdma-mm2s-channel"; 101 interrupts = < 0 54 4 >; 102 xlnx,datawidth = <0x40>; 103 } ; 104 dma-channel@40030030 { 105 compatible = "xlnx,axi-vdma-s2mm-channel"; 106 interrupts = < 0 53 4 >; 107 xlnx,datawidth = <0x40>; 108 } ; 109} ; 110 111 112* DMA client 113 114Required properties: 115- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs, 116 where Channel ID is '0' for write/tx and '1' for read/rx 117 channel. For MCMDA, MM2S channel(write/tx) ID start from 118 '0' and is in [0-15] range. S2MM channel(read/rx) ID start 119 from '16' and is in [16-31] range. These channels ID are 120 fixed irrespective of IP configuration. 121 122- dma-names: a list of DMA channel names, one per "dmas" entry 123 124Example: 125++++++++ 126 127vdmatest_0: vdmatest@0 { 128 compatible ="xlnx,axi-vdma-test-1.00.a"; 129 dmas = <&axi_vdma_0 0 130 &axi_vdma_0 1>; 131 dma-names = "vdma0", "vdma1"; 132} ; 133