1Xilinx AXI VDMA engine, it does transfers between memory and video devices.
2It can be configured to have one channel or two channels. If configured
3as two channels, one is to transmit to the video device and another is
4to receive from the video device.
5
6Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream
7target devices. It can be configured to have one channel or two channels.
8If configured as two channels, one is to transmit to the device and another
9is to receive from the device.
10
11Xilinx AXI CDMA engine, it does transfers between memory-mapped source
12address and a memory-mapped destination address.
13
14Required properties:
15- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or
16	      "xlnx,axi-cdma-1.00.a""
17- #dma-cells: Should be <1>, see "dmas" property below
18- reg: Should contain VDMA registers location and length.
19- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits).
20- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>.
21- dma-channel child node: Should have at least one channel and can have up to
22	two channels per device. This node specifies the properties of each
23	DMA channel (see child node properties below).
24- clocks: Input clock specifier. Refer to common clock bindings.
25- clock-names: List of input clocks
26	For VDMA:
27	Required elements: "s_axi_lite_aclk"
28	Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk",
29			   "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"
30	For CDMA:
31	Required elements: "s_axi_lite_aclk", "m_axi_aclk"
32	FOR AXIDMA:
33	Required elements: "s_axi_lite_aclk"
34	Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
35			   "m_axi_sg_aclk"
36
37Required properties for VDMA:
38- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w.
39
40Optional properties:
41- xlnx,include-sg: Tells configured for Scatter-mode in
42	the hardware.
43Optional properties for AXI DMA:
44- xlnx,sg-length-width: Should be set to the width in bits of the length
45	register as configured in h/w. Takes values {8...26}. If the property
46	is missing or invalid then the default value 23 is used. This is the
47	maximum value that is supported by all IP versions.
48- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware.
49Optional properties for VDMA:
50- xlnx,flush-fsync: Tells which channel to Flush on Frame sync.
51	It takes following values:
52	{1}, flush both channels
53	{2}, flush mm2s channel
54	{3}, flush s2mm channel
55
56Required child node properties:
57- compatible:
58	For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or
59	"xlnx,axi-vdma-s2mm-channel".
60	For CDMA: It should be "xlnx,axi-cdma-channel".
61	For AXIDMA: It should be either "xlnx,axi-dma-mm2s-channel" or
62	"xlnx,axi-dma-s2mm-channel".
63- interrupts: Should contain per channel VDMA interrupts.
64- xlnx,datawidth: Should contain the stream data width, take values
65	{32,64...1024}.
66
67Optional child node properties:
68- xlnx,include-dre: Tells hardware is configured for Data
69	Realignment Engine.
70Optional child node properties for VDMA:
71- xlnx,genlock-mode: Tells Genlock synchronization is
72	enabled/disabled in hardware.
73- xlnx,enable-vert-flip: Tells vertical flip is
74	enabled/disabled in hardware(S2MM path).
75Optional child node properties for AXI DMA:
76-dma-channels: Number of dma channels in child node.
77
78Example:
79++++++++
80
81axi_vdma_0: axivdma@40030000 {
82	compatible = "xlnx,axi-vdma-1.00.a";
83	#dma_cells = <1>;
84	reg = < 0x40030000 0x10000 >;
85	dma-ranges = <0x00000000 0x00000000 0x40000000>;
86	xlnx,num-fstores = <0x8>;
87	xlnx,flush-fsync = <0x1>;
88	xlnx,addrwidth = <0x20>;
89	clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>;
90	clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk",
91		      "m_axis_mm2s_aclk", "s_axis_s2mm_aclk";
92	dma-channel@40030000 {
93		compatible = "xlnx,axi-vdma-mm2s-channel";
94		interrupts = < 0 54 4 >;
95		xlnx,datawidth = <0x40>;
96	} ;
97	dma-channel@40030030 {
98		compatible = "xlnx,axi-vdma-s2mm-channel";
99		interrupts = < 0 53 4 >;
100		xlnx,datawidth = <0x40>;
101	} ;
102} ;
103
104
105* DMA client
106
107Required properties:
108- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs,
109	where Channel ID is '0' for write/tx and '1' for read/rx
110	channel.
111- dma-names: a list of DMA channel names, one per "dmas" entry
112
113Example:
114++++++++
115
116vdmatest_0: vdmatest@0 {
117	compatible ="xlnx,axi-vdma-test-1.00.a";
118	dmas = <&axi_vdma_0 0
119		&axi_vdma_0 1>;
120	dma-names = "vdma0", "vdma1";
121} ;
122