1Xilinx AXI VDMA engine, it does transfers between memory and video devices. 2It can be configured to have one channel or two channels. If configured 3as two channels, one is to transmit to the video device and another is 4to receive from the video device. 5 6Xilinx AXI DMA engine, it does transfers between memory and AXI4 stream 7target devices. It can be configured to have one channel or two channels. 8If configured as two channels, one is to transmit to the device and another 9is to receive from the device. 10 11Xilinx AXI CDMA engine, it does transfers between memory-mapped source 12address and a memory-mapped destination address. 13 14Required properties: 15- compatible: Should be one of- 16 "xlnx,axi-vdma-1.00.a" 17 "xlnx,axi-dma-1.00.a" 18 "xlnx,axi-cdma-1.00.a" 19- #dma-cells: Should be <1>, see "dmas" property below 20- reg: Should contain VDMA registers location and length. 21- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits). 22- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>. 23- dma-channel child node: Should have at least one channel and can have up to 24 two channels per device. This node specifies the properties of each 25 DMA channel (see child node properties below). 26- clocks: Input clock specifier. Refer to common clock bindings. 27- clock-names: List of input clocks 28 For VDMA: 29 Required elements: "s_axi_lite_aclk" 30 Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk", 31 "m_axis_mm2s_aclk", "s_axis_s2mm_aclk" 32 For CDMA: 33 Required elements: "s_axi_lite_aclk", "m_axi_aclk" 34 For AXIDMA: 35 Required elements: "s_axi_lite_aclk" 36 Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", 37 "m_axi_sg_aclk" 38 39Required properties for VDMA: 40- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. 41 42Optional properties for AXI DMA: 43- xlnx,sg-length-width: Should be set to the width in bits of the length 44 register as configured in h/w. Takes values {8...26}. If the property 45 is missing or invalid then the default value 23 is used. This is the 46 maximum value that is supported by all IP versions. 47Optional properties for VDMA: 48- xlnx,flush-fsync: Tells which channel to Flush on Frame sync. 49 It takes following values: 50 {1}, flush both channels 51 {2}, flush mm2s channel 52 {3}, flush s2mm channel 53 54Required child node properties: 55- compatible: 56 For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or 57 "xlnx,axi-vdma-s2mm-channel". 58 For CDMA: It should be "xlnx,axi-cdma-channel". 59 For AXIDMA: It should be either "xlnx,axi-dma-mm2s-channel" or 60 "xlnx,axi-dma-s2mm-channel". 61- interrupts: Should contain per channel VDMA interrupts. 62- xlnx,datawidth: Should contain the stream data width, take values 63 {32,64...1024}. 64 65Optional child node properties: 66- xlnx,include-dre: Tells hardware is configured for Data 67 Realignment Engine. 68Optional child node properties for VDMA: 69- xlnx,genlock-mode: Tells Genlock synchronization is 70 enabled/disabled in hardware. 71- xlnx,enable-vert-flip: Tells vertical flip is 72 enabled/disabled in hardware(S2MM path). 73 74Example: 75++++++++ 76 77axi_vdma_0: axivdma@40030000 { 78 compatible = "xlnx,axi-vdma-1.00.a"; 79 #dma_cells = <1>; 80 reg = < 0x40030000 0x10000 >; 81 dma-ranges = <0x00000000 0x00000000 0x40000000>; 82 xlnx,num-fstores = <0x8>; 83 xlnx,flush-fsync = <0x1>; 84 xlnx,addrwidth = <0x20>; 85 clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>; 86 clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", 87 "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"; 88 dma-channel@40030000 { 89 compatible = "xlnx,axi-vdma-mm2s-channel"; 90 interrupts = < 0 54 4 >; 91 xlnx,datawidth = <0x40>; 92 } ; 93 dma-channel@40030030 { 94 compatible = "xlnx,axi-vdma-s2mm-channel"; 95 interrupts = < 0 53 4 >; 96 xlnx,datawidth = <0x40>; 97 } ; 98} ; 99 100 101* DMA client 102 103Required properties: 104- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs, 105 where Channel ID is '0' for write/tx and '1' for read/rx 106 channel. 107- dma-names: a list of DMA channel names, one per "dmas" entry 108 109Example: 110++++++++ 111 112vdmatest_0: vdmatest@0 { 113 compatible ="xlnx,axi-vdma-test-1.00.a"; 114 dmas = <&axi_vdma_0 0 115 &axi_vdma_0 1>; 116 dma-names = "vdma0", "vdma1"; 117} ; 118