1fde57a7cSKedareswara rao AppanaXilinx AXI VDMA engine, it does transfers between memory and video devices. 2fde57a7cSKedareswara rao AppanaIt can be configured to have one channel or two channels. If configured 3fde57a7cSKedareswara rao Appanaas two channels, one is to transmit to the video device and another is 4fde57a7cSKedareswara rao Appanato receive from the video device. 5fde57a7cSKedareswara rao Appana 6fde57a7cSKedareswara rao AppanaXilinx AXI DMA engine, it does transfers between memory and AXI4 stream 7fde57a7cSKedareswara rao Appanatarget devices. It can be configured to have one channel or two channels. 8fde57a7cSKedareswara rao AppanaIf configured as two channels, one is to transmit to the device and another 9fde57a7cSKedareswara rao Appanais to receive from the device. 10fde57a7cSKedareswara rao Appana 11fde57a7cSKedareswara rao AppanaXilinx AXI CDMA engine, it does transfers between memory-mapped source 12fde57a7cSKedareswara rao Appanaaddress and a memory-mapped destination address. 13fde57a7cSKedareswara rao Appana 14fde57a7cSKedareswara rao AppanaRequired properties: 15fde57a7cSKedareswara rao Appana- compatible: Should be "xlnx,axi-vdma-1.00.a" or "xlnx,axi-dma-1.00.a" or 16fde57a7cSKedareswara rao Appana "xlnx,axi-cdma-1.00.a"" 17fde57a7cSKedareswara rao Appana- #dma-cells: Should be <1>, see "dmas" property below 18fde57a7cSKedareswara rao Appana- reg: Should contain VDMA registers location and length. 19fde57a7cSKedareswara rao Appana- xlnx,addrwidth: Should be the vdma addressing size in bits(ex: 32 bits). 20fde57a7cSKedareswara rao Appana- dma-ranges: Should be as the following <dma_addr cpu_addr max_len>. 21fde57a7cSKedareswara rao Appana- dma-channel child node: Should have at least one channel and can have up to 22fde57a7cSKedareswara rao Appana two channels per device. This node specifies the properties of each 23fde57a7cSKedareswara rao Appana DMA channel (see child node properties below). 24fde57a7cSKedareswara rao Appana- clocks: Input clock specifier. Refer to common clock bindings. 25fde57a7cSKedareswara rao Appana- clock-names: List of input clocks 26fde57a7cSKedareswara rao Appana For VDMA: 27fde57a7cSKedareswara rao Appana Required elements: "s_axi_lite_aclk" 28fde57a7cSKedareswara rao Appana Optional elements: "m_axi_mm2s_aclk" "m_axi_s2mm_aclk", 29fde57a7cSKedareswara rao Appana "m_axis_mm2s_aclk", "s_axis_s2mm_aclk" 30fde57a7cSKedareswara rao Appana For CDMA: 31fde57a7cSKedareswara rao Appana Required elements: "s_axi_lite_aclk", "m_axi_aclk" 32fde57a7cSKedareswara rao Appana FOR AXIDMA: 33fde57a7cSKedareswara rao Appana Required elements: "s_axi_lite_aclk" 34fde57a7cSKedareswara rao Appana Optional elements: "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", 35fde57a7cSKedareswara rao Appana "m_axi_sg_aclk" 36fde57a7cSKedareswara rao Appana 37fde57a7cSKedareswara rao AppanaRequired properties for VDMA: 38fde57a7cSKedareswara rao Appana- xlnx,num-fstores: Should be the number of framebuffers as configured in h/w. 39fde57a7cSKedareswara rao Appana 40fde57a7cSKedareswara rao AppanaOptional properties: 41fde57a7cSKedareswara rao Appana- xlnx,include-sg: Tells configured for Scatter-mode in 42fde57a7cSKedareswara rao Appana the hardware. 43fde57a7cSKedareswara rao AppanaOptional properties for AXI DMA: 447df54dbeSAndrea Merello- xlnx,sg-length-width: Should be set to the width in bits of the length 457df54dbeSAndrea Merello register as configured in h/w. Takes values {8...26}. If the property 467df54dbeSAndrea Merello is missing or invalid then the default value 23 is used. This is the 477df54dbeSAndrea Merello maximum value that is supported by all IP versions. 48fde57a7cSKedareswara rao Appana- xlnx,mcdma: Tells whether configured for multi-channel mode in the hardware. 49fde57a7cSKedareswara rao AppanaOptional properties for VDMA: 50fde57a7cSKedareswara rao Appana- xlnx,flush-fsync: Tells which channel to Flush on Frame sync. 51fde57a7cSKedareswara rao Appana It takes following values: 52fde57a7cSKedareswara rao Appana {1}, flush both channels 53fde57a7cSKedareswara rao Appana {2}, flush mm2s channel 54fde57a7cSKedareswara rao Appana {3}, flush s2mm channel 55fde57a7cSKedareswara rao Appana 56fde57a7cSKedareswara rao AppanaRequired child node properties: 57e131f1baSKedareswara rao Appana- compatible: 58e131f1baSKedareswara rao Appana For VDMA: It should be either "xlnx,axi-vdma-mm2s-channel" or 59fde57a7cSKedareswara rao Appana "xlnx,axi-vdma-s2mm-channel". 60e131f1baSKedareswara rao Appana For CDMA: It should be "xlnx,axi-cdma-channel". 61e131f1baSKedareswara rao Appana For AXIDMA: It should be either "xlnx,axi-dma-mm2s-channel" or 62e131f1baSKedareswara rao Appana "xlnx,axi-dma-s2mm-channel". 63fde57a7cSKedareswara rao Appana- interrupts: Should contain per channel VDMA interrupts. 64fde57a7cSKedareswara rao Appana- xlnx,datawidth: Should contain the stream data width, take values 65fde57a7cSKedareswara rao Appana {32,64...1024}. 66fde57a7cSKedareswara rao Appana 67fde57a7cSKedareswara rao AppanaOptional child node properties: 68fde57a7cSKedareswara rao Appana- xlnx,include-dre: Tells hardware is configured for Data 69fde57a7cSKedareswara rao Appana Realignment Engine. 70fde57a7cSKedareswara rao AppanaOptional child node properties for VDMA: 71fde57a7cSKedareswara rao Appana- xlnx,genlock-mode: Tells Genlock synchronization is 72fde57a7cSKedareswara rao Appana enabled/disabled in hardware. 73714b8392SRadhey Shyam Pandey- xlnx,enable-vert-flip: Tells vertical flip is 74714b8392SRadhey Shyam Pandey enabled/disabled in hardware(S2MM path). 75fde57a7cSKedareswara rao AppanaOptional child node properties for AXI DMA: 76fde57a7cSKedareswara rao Appana-dma-channels: Number of dma channels in child node. 77fde57a7cSKedareswara rao Appana 78fde57a7cSKedareswara rao AppanaExample: 79fde57a7cSKedareswara rao Appana++++++++ 80fde57a7cSKedareswara rao Appana 81fde57a7cSKedareswara rao Appanaaxi_vdma_0: axivdma@40030000 { 82fde57a7cSKedareswara rao Appana compatible = "xlnx,axi-vdma-1.00.a"; 83fde57a7cSKedareswara rao Appana #dma_cells = <1>; 84fde57a7cSKedareswara rao Appana reg = < 0x40030000 0x10000 >; 85fde57a7cSKedareswara rao Appana dma-ranges = <0x00000000 0x00000000 0x40000000>; 86fde57a7cSKedareswara rao Appana xlnx,num-fstores = <0x8>; 87fde57a7cSKedareswara rao Appana xlnx,flush-fsync = <0x1>; 88fde57a7cSKedareswara rao Appana xlnx,addrwidth = <0x20>; 89fde57a7cSKedareswara rao Appana clocks = <&clk 0>, <&clk 1>, <&clk 2>, <&clk 3>, <&clk 4>; 90fde57a7cSKedareswara rao Appana clock-names = "s_axi_lite_aclk", "m_axi_mm2s_aclk", "m_axi_s2mm_aclk", 91fde57a7cSKedareswara rao Appana "m_axis_mm2s_aclk", "s_axis_s2mm_aclk"; 92fde57a7cSKedareswara rao Appana dma-channel@40030000 { 93fde57a7cSKedareswara rao Appana compatible = "xlnx,axi-vdma-mm2s-channel"; 94fde57a7cSKedareswara rao Appana interrupts = < 0 54 4 >; 95fde57a7cSKedareswara rao Appana xlnx,datawidth = <0x40>; 96fde57a7cSKedareswara rao Appana } ; 97fde57a7cSKedareswara rao Appana dma-channel@40030030 { 98fde57a7cSKedareswara rao Appana compatible = "xlnx,axi-vdma-s2mm-channel"; 99fde57a7cSKedareswara rao Appana interrupts = < 0 53 4 >; 100fde57a7cSKedareswara rao Appana xlnx,datawidth = <0x40>; 101fde57a7cSKedareswara rao Appana } ; 102fde57a7cSKedareswara rao Appana} ; 103fde57a7cSKedareswara rao Appana 104fde57a7cSKedareswara rao Appana 105fde57a7cSKedareswara rao Appana* DMA client 106fde57a7cSKedareswara rao Appana 107fde57a7cSKedareswara rao AppanaRequired properties: 108fde57a7cSKedareswara rao Appana- dmas: a list of <[Video DMA device phandle] [Channel ID]> pairs, 109fde57a7cSKedareswara rao Appana where Channel ID is '0' for write/tx and '1' for read/rx 110fde57a7cSKedareswara rao Appana channel. 111fde57a7cSKedareswara rao Appana- dma-names: a list of DMA channel names, one per "dmas" entry 112fde57a7cSKedareswara rao Appana 113fde57a7cSKedareswara rao AppanaExample: 114fde57a7cSKedareswara rao Appana++++++++ 115fde57a7cSKedareswara rao Appana 116fde57a7cSKedareswara rao Appanavdmatest_0: vdmatest@0 { 117fde57a7cSKedareswara rao Appana compatible ="xlnx,axi-vdma-test-1.00.a"; 118fde57a7cSKedareswara rao Appana dmas = <&axi_vdma_0 0 119fde57a7cSKedareswara rao Appana &axi_vdma_0 1>; 120fde57a7cSKedareswara rao Appana dma-names = "vdma0", "vdma1"; 121fde57a7cSKedareswara rao Appana} ; 122