1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Texas Instruments K3 NAVSS Unified DMA Device Tree Bindings
8
9maintainers:
10  - Peter Ujfalusi <peter.ujfalusi@ti.com>
11
12description: |
13  The UDMA-P is intended to perform similar (but significantly upgraded)
14  functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
15  module supports the transmission and reception of various packet types.
16  The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
17  data structure compliant packets to/from smaller data blocks that are natively
18  compatible with the specific requirements of each connected peripheral.
19  Multiple Tx and Rx channels are provided within the DMA which allow multiple
20  segmentation or reassembly operations to be ongoing. The DMA controller
21  maintains state information for each of the channels which allows packet
22  segmentation and reassembly operations to be time division multiplexed between
23  channels in order to share the underlying DMA hardware. An external DMA
24  scheduler is used to control the ordering and rate at which this multiplexing
25  occurs for Transmit operations. The ordering and rate of Receive operations
26  is indirectly controlled by the order in which blocks are pushed into the DMA
27  on the Rx PSI-L interface.
28
29  The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
30  channels. Channels in the UDMA-P can be configured to be either Packet-Based
31  or Third-Party channels on a channel by channel basis.
32
33  All transfers within NAVSS is done between PSI-L source and destination
34  threads.
35  The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or
36  legacy, non PSI-L native peripherals. In the later case a special, small PDMA
37  is tasked to act as a bridge between the PSI-L fabric and the legacy
38  peripheral.
39
40  PDMAs can be configured via UDMAP peer registers to match with the
41  configuration of the legacy peripheral.
42
43allOf:
44  - $ref: "../dma-controller.yaml#"
45
46properties:
47  "#dma-cells":
48    minimum: 1
49    maximum: 2
50    description: |
51      The cell is the PSI-L  thread ID of the remote (to UDMAP) end.
52      Valid ranges for thread ID depends on the data movement direction:
53      for source thread IDs (rx): 0 - 0x7fff
54      for destination thread IDs (tx): 0x8000 - 0xffff
55
56      Please refer to the device documentation for the PSI-L thread map and also
57      the PSI-L peripheral chapter for the correct thread ID.
58
59      When #dma-cells is 2, the second parameter is the channel ATYPE.
60
61  compatible:
62    enum:
63      - ti,am654-navss-main-udmap
64      - ti,am654-navss-mcu-udmap
65      - ti,j721e-navss-main-udmap
66      - ti,j721e-navss-mcu-udmap
67
68  reg:
69    maxItems: 3
70
71  reg-names:
72   items:
73     - const: gcfg
74     - const: rchanrt
75     - const: tchanrt
76
77  msi-parent: true
78
79  ti,sci:
80    description: phandle to TI-SCI compatible System controller node
81    allOf:
82      - $ref: /schemas/types.yaml#/definitions/phandle
83
84  ti,sci-dev-id:
85    description: TI-SCI device id of UDMAP
86    allOf:
87      - $ref: /schemas/types.yaml#/definitions/uint32
88
89  ti,ringacc:
90    description: phandle to the ring accelerator node
91    allOf:
92      - $ref: /schemas/types.yaml#/definitions/phandle
93
94  ti,sci-rm-range-tchan:
95    description: |
96      Array of UDMA tchan resource subtypes for resource allocation for this
97      host
98    allOf:
99      - $ref: /schemas/types.yaml#/definitions/uint32-array
100    minItems: 1
101    # Should be enough
102    maxItems: 255
103
104  ti,sci-rm-range-rchan:
105    description: |
106      Array of UDMA rchan resource subtypes for resource allocation for this
107      host
108    allOf:
109      - $ref: /schemas/types.yaml#/definitions/uint32-array
110    minItems: 1
111    # Should be enough
112    maxItems: 255
113
114  ti,sci-rm-range-rflow:
115    description: |
116      Array of UDMA rflow resource subtypes for resource allocation for this
117      host
118    allOf:
119      - $ref: /schemas/types.yaml#/definitions/uint32-array
120    minItems: 1
121    # Should be enough
122    maxItems: 255
123
124required:
125  - compatible
126  - "#dma-cells"
127  - reg
128  - reg-names
129  - msi-parent
130  - ti,sci
131  - ti,sci-dev-id
132  - ti,ringacc
133  - ti,sci-rm-range-tchan
134  - ti,sci-rm-range-rchan
135  - ti,sci-rm-range-rflow
136
137if:
138  properties:
139    "#dma-cells":
140      const: 2
141then:
142  properties:
143    ti,udma-atype:
144      description: ATYPE value which should be used by non slave channels
145      allOf:
146        - $ref: /schemas/types.yaml#/definitions/uint32
147
148  required:
149    - ti,udma-atype
150
151examples:
152  - |+
153    cbass_main {
154        #address-cells = <2>;
155        #size-cells = <2>;
156
157        cbass_main_navss: navss@30800000 {
158            compatible = "simple-mfd";
159            #address-cells = <2>;
160            #size-cells = <2>;
161            dma-coherent;
162            dma-ranges;
163            ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>;
164
165            ti,sci-dev-id = <118>;
166
167            main_udmap: dma-controller@31150000 {
168                compatible = "ti,am654-navss-main-udmap";
169                reg = <0x0 0x31150000 0x0 0x100>,
170                      <0x0 0x34000000 0x0 0x100000>,
171                      <0x0 0x35000000 0x0 0x100000>;
172                reg-names = "gcfg", "rchanrt", "tchanrt";
173                #dma-cells = <1>;
174
175                ti,ringacc = <&ringacc>;
176
177                msi-parent = <&inta_main_udmass>;
178
179                ti,sci = <&dmsc>;
180                ti,sci-dev-id = <188>;
181
182                ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
183                                        <0x2>; /* TX_CHAN */
184                ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
185                                        <0x5>; /* RX_CHAN */
186                ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
187            };
188        };
189    };
190