1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Texas Instruments K3 NAVSS Unified DMA Device Tree Bindings
8
9maintainers:
10  - Peter Ujfalusi <peter.ujfalusi@ti.com>
11
12description: |
13  The UDMA-P is intended to perform similar (but significantly upgraded)
14  functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
15  module supports the transmission and reception of various packet types.
16  The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
17  data structure compliant packets to/from smaller data blocks that are natively
18  compatible with the specific requirements of each connected peripheral.
19  Multiple Tx and Rx channels are provided within the DMA which allow multiple
20  segmentation or reassembly operations to be ongoing. The DMA controller
21  maintains state information for each of the channels which allows packet
22  segmentation and reassembly operations to be time division multiplexed between
23  channels in order to share the underlying DMA hardware. An external DMA
24  scheduler is used to control the ordering and rate at which this multiplexing
25  occurs for Transmit operations. The ordering and rate of Receive operations
26  is indirectly controlled by the order in which blocks are pushed into the DMA
27  on the Rx PSI-L interface.
28
29  The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
30  channels. Channels in the UDMA-P can be configured to be either Packet-Based
31  or Third-Party channels on a channel by channel basis.
32
33  All transfers within NAVSS is done between PSI-L source and destination
34  threads.
35  The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or
36  legacy, non PSI-L native peripherals. In the later case a special, small PDMA
37  is tasked to act as a bridge between the PSI-L fabric and the legacy
38  peripheral.
39
40  PDMAs can be configured via UDMAP peer registers to match with the
41  configuration of the legacy peripheral.
42
43allOf:
44  - $ref: "../dma-controller.yaml#"
45
46properties:
47  "#dma-cells":
48    const: 1
49    description: |
50      The cell is the PSI-L  thread ID of the remote (to UDMAP) end.
51      Valid ranges for thread ID depends on the data movement direction:
52      for source thread IDs (rx): 0 - 0x7fff
53      for destination thread IDs (tx): 0x8000 - 0xffff
54
55      Please refer to the device documentation for the PSI-L thread map and also
56      the PSI-L peripheral chapter for the correct thread ID.
57
58  compatible:
59    enum:
60      - ti,am654-navss-main-udmap
61      - ti,am654-navss-mcu-udmap
62      - ti,j721e-navss-main-udmap
63      - ti,j721e-navss-mcu-udmap
64
65  reg:
66    maxItems: 3
67
68  reg-names:
69   items:
70     - const: gcfg
71     - const: rchanrt
72     - const: tchanrt
73
74  msi-parent: true
75
76  ti,sci:
77    description: phandle to TI-SCI compatible System controller node
78    allOf:
79      - $ref: /schemas/types.yaml#/definitions/phandle
80
81  ti,sci-dev-id:
82    description: TI-SCI device id of UDMAP
83    allOf:
84      - $ref: /schemas/types.yaml#/definitions/uint32
85
86  ti,ringacc:
87    description: phandle to the ring accelerator node
88    allOf:
89      - $ref: /schemas/types.yaml#/definitions/phandle
90
91  ti,sci-rm-range-tchan:
92    description: |
93      Array of UDMA tchan resource subtypes for resource allocation for this
94      host
95    allOf:
96      - $ref: /schemas/types.yaml#/definitions/uint32-array
97    minItems: 1
98    # Should be enough
99    maxItems: 255
100
101  ti,sci-rm-range-rchan:
102    description: |
103      Array of UDMA rchan resource subtypes for resource allocation for this
104      host
105    allOf:
106      - $ref: /schemas/types.yaml#/definitions/uint32-array
107    minItems: 1
108    # Should be enough
109    maxItems: 255
110
111  ti,sci-rm-range-rflow:
112    description: |
113      Array of UDMA rflow resource subtypes for resource allocation for this
114      host
115    allOf:
116      - $ref: /schemas/types.yaml#/definitions/uint32-array
117    minItems: 1
118    # Should be enough
119    maxItems: 255
120
121required:
122  - compatible
123  - "#dma-cells"
124  - reg
125  - reg-names
126  - msi-parent
127  - ti,sci
128  - ti,sci-dev-id
129  - ti,ringacc
130  - ti,sci-rm-range-tchan
131  - ti,sci-rm-range-rchan
132  - ti,sci-rm-range-rflow
133
134examples:
135  - |+
136    cbass_main {
137        #address-cells = <2>;
138        #size-cells = <2>;
139
140        cbass_main_navss: navss@30800000 {
141            compatible = "simple-mfd";
142            #address-cells = <2>;
143            #size-cells = <2>;
144            dma-coherent;
145            dma-ranges;
146            ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>;
147
148            ti,sci-dev-id = <118>;
149
150            main_udmap: dma-controller@31150000 {
151                compatible = "ti,am654-navss-main-udmap";
152                reg = <0x0 0x31150000 0x0 0x100>,
153                      <0x0 0x34000000 0x0 0x100000>,
154                      <0x0 0x35000000 0x0 0x100000>;
155                reg-names = "gcfg", "rchanrt", "tchanrt";
156                #dma-cells = <1>;
157
158                ti,ringacc = <&ringacc>;
159
160                msi-parent = <&inta_main_udmass>;
161
162                ti,sci = <&dmsc>;
163                ti,sci-dev-id = <188>;
164
165                ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
166                                        <0x2>; /* TX_CHAN */
167                ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
168                                        <0x5>; /* RX_CHAN */
169                ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
170            };
171        };
172    };
173