1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/ti/k3-udma.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Texas Instruments K3 NAVSS Unified DMA Device Tree Bindings
8
9maintainers:
10  - Peter Ujfalusi <peter.ujfalusi@ti.com>
11
12description: |
13  The UDMA-P is intended to perform similar (but significantly upgraded)
14  functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P
15  module supports the transmission and reception of various packet types.
16  The UDMA-P architecture facilitates the segmentation and reassembly of SoC DMA
17  data structure compliant packets to/from smaller data blocks that are natively
18  compatible with the specific requirements of each connected peripheral.
19  Multiple Tx and Rx channels are provided within the DMA which allow multiple
20  segmentation or reassembly operations to be ongoing. The DMA controller
21  maintains state information for each of the channels which allows packet
22  segmentation and reassembly operations to be time division multiplexed between
23  channels in order to share the underlying DMA hardware. An external DMA
24  scheduler is used to control the ordering and rate at which this multiplexing
25  occurs for Transmit operations. The ordering and rate of Receive operations
26  is indirectly controlled by the order in which blocks are pushed into the DMA
27  on the Rx PSI-L interface.
28
29  The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
30  channels. Channels in the UDMA-P can be configured to be either Packet-Based
31  or Third-Party channels on a channel by channel basis.
32
33  All transfers within NAVSS is done between PSI-L source and destination
34  threads.
35  The peripherals serviced by UDMA can be PSI-L native (sa2ul, cpsw, etc) or
36  legacy, non PSI-L native peripherals. In the later case a special, small PDMA
37  is tasked to act as a bridge between the PSI-L fabric and the legacy
38  peripheral.
39
40  PDMAs can be configured via UDMAP peer registers to match with the
41  configuration of the legacy peripheral.
42
43allOf:
44  - $ref: "../dma-controller.yaml#"
45
46properties:
47  "#dma-cells":
48    minimum: 1
49    maximum: 2
50    description: |
51      The cell is the PSI-L  thread ID of the remote (to UDMAP) end.
52      Valid ranges for thread ID depends on the data movement direction:
53      for source thread IDs (rx): 0 - 0x7fff
54      for destination thread IDs (tx): 0x8000 - 0xffff
55
56      Please refer to the device documentation for the PSI-L thread map and also
57      the PSI-L peripheral chapter for the correct thread ID.
58
59      When #dma-cells is 2, the second parameter is the channel ATYPE.
60
61  compatible:
62    enum:
63      - ti,am654-navss-main-udmap
64      - ti,am654-navss-mcu-udmap
65      - ti,j721e-navss-main-udmap
66      - ti,j721e-navss-mcu-udmap
67
68  reg:
69    maxItems: 3
70
71  reg-names:
72    items:
73      - const: gcfg
74      - const: rchanrt
75      - const: tchanrt
76
77  msi-parent: true
78
79  ti,sci:
80    description: phandle to TI-SCI compatible System controller node
81    $ref: /schemas/types.yaml#/definitions/phandle
82
83  ti,sci-dev-id:
84    description: TI-SCI device id of UDMAP
85    $ref: /schemas/types.yaml#/definitions/uint32
86
87  ti,ringacc:
88    description: phandle to the ring accelerator node
89    $ref: /schemas/types.yaml#/definitions/phandle
90
91  ti,sci-rm-range-tchan:
92    description: |
93      Array of UDMA tchan resource subtypes for resource allocation for this
94      host
95    $ref: /schemas/types.yaml#/definitions/uint32-array
96    minItems: 1
97    # Should be enough
98    maxItems: 255
99
100  ti,sci-rm-range-rchan:
101    description: |
102      Array of UDMA rchan resource subtypes for resource allocation for this
103      host
104    $ref: /schemas/types.yaml#/definitions/uint32-array
105    minItems: 1
106    # Should be enough
107    maxItems: 255
108
109  ti,sci-rm-range-rflow:
110    description: |
111      Array of UDMA rflow resource subtypes for resource allocation for this
112      host
113    $ref: /schemas/types.yaml#/definitions/uint32-array
114    minItems: 1
115    # Should be enough
116    maxItems: 255
117
118required:
119  - compatible
120  - "#dma-cells"
121  - reg
122  - reg-names
123  - msi-parent
124  - ti,sci
125  - ti,sci-dev-id
126  - ti,ringacc
127  - ti,sci-rm-range-tchan
128  - ti,sci-rm-range-rchan
129  - ti,sci-rm-range-rflow
130
131if:
132  properties:
133    "#dma-cells":
134      const: 2
135then:
136  properties:
137    ti,udma-atype:
138      description: ATYPE value which should be used by non slave channels
139      $ref: /schemas/types.yaml#/definitions/uint32
140
141  required:
142    - ti,udma-atype
143
144examples:
145  - |+
146    cbass_main {
147        #address-cells = <2>;
148        #size-cells = <2>;
149
150        cbass_main_navss: navss@30800000 {
151            compatible = "simple-mfd";
152            #address-cells = <2>;
153            #size-cells = <2>;
154            dma-coherent;
155            dma-ranges;
156            ranges = <0x0 0x30800000 0x0 0x30800000 0x0 0x05000000>;
157
158            ti,sci-dev-id = <118>;
159
160            main_udmap: dma-controller@31150000 {
161                compatible = "ti,am654-navss-main-udmap";
162                reg = <0x0 0x31150000 0x0 0x100>,
163                      <0x0 0x34000000 0x0 0x100000>,
164                      <0x0 0x35000000 0x0 0x100000>;
165                reg-names = "gcfg", "rchanrt", "tchanrt";
166                #dma-cells = <1>;
167
168                ti,ringacc = <&ringacc>;
169
170                msi-parent = <&inta_main_udmass>;
171
172                ti,sci = <&dmsc>;
173                ti,sci-dev-id = <188>;
174
175                ti,sci-rm-range-tchan = <0x1>, /* TX_HCHAN */
176                                        <0x2>; /* TX_CHAN */
177                ti,sci-rm-range-rchan = <0x4>, /* RX_HCHAN */
178                                        <0x5>; /* RX_CHAN */
179                ti,sci-rm-range-rflow = <0x6>; /* GP RFLOW */
180            };
181        };
182    };
183