1Texas Instruments eDMA
2
3The eDMA3 consists of two components: Channel controller (CC) and Transfer
4Controller(s) (TC). The CC is the main entry for DMA users since it is
5responsible for the DMA channel handling, while the TCs are responsible to
6execute the actual DMA tansfer.
7
8------------------------------------------------------------------------------
9eDMA3 Channel Controller
10
11Required properties:
12- compatible:	"ti,edma3-tpcc" for the channel controller(s)
13- #dma-cells:	Should be set to <2>. The first number is the DMA request
14		number and the second is the TC the channel is serviced on.
15- reg:		Memory map of eDMA CC
16- reg-names:	"edma3_cc"
17- interrupts:	Interrupt lines for CCINT, MPERR and CCERRINT.
18- interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
19- ti,tptcs:	List of TPTCs associated with the eDMA in the following form:
20		<&tptc_phandle TC_priority_number>. The highest priority is 0.
21
22Optional properties:
23- ti,hwmods:	Name of the hwmods associated to the eDMA CC
24- ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
25		these channels will be SW triggered channels. See example.
26- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
27		the driver, they are allocated to be used by for example the
28		DSP. See example.
29
30------------------------------------------------------------------------------
31eDMA3 Transfer Controller
32
33Required properties:
34- compatible:	"ti,edma3-tptc" for the transfer controller(s)
35- reg:		Memory map of eDMA TC
36- interrupts:	Interrupt number for TCerrint.
37
38Optional properties:
39- ti,hwmods:	Name of the hwmods associated to the given eDMA TC
40- interrupt-names: "edma3_tcerrint"
41
42------------------------------------------------------------------------------
43Example:
44
45edma: edma@49000000 {
46	compatible = "ti,edma3-tpcc";
47	ti,hwmods = "tpcc";
48	reg =	<0x49000000 0x10000>;
49	reg-names = "edma3_cc";
50	interrupts = <12 13 14>;
51	interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
52	dma-requests = <64>;
53	#dma-cells = <2>;
54
55	ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>;
56
57	/* Channel 20 and 21 is allocated for memcpy */
58	ti,edma-memcpy-channels = <20 21>;
59	/* The following PaRAM slots are reserved: 35-44 and 100-109 */
60	ti,edma-reserved-slot-ranges = <35 10>, <100 10>;
61};
62
63edma_tptc0: tptc@49800000 {
64	compatible = "ti,edma3-tptc";
65	ti,hwmods = "tptc0";
66	reg =	<0x49800000 0x100000>;
67	interrupts = <112>;
68	interrupt-names = "edm3_tcerrint";
69};
70
71edma_tptc1: tptc@49900000 {
72	compatible = "ti,edma3-tptc";
73	ti,hwmods = "tptc1";
74	reg =	<0x49900000 0x100000>;
75	interrupts = <113>;
76	interrupt-names = "edm3_tcerrint";
77};
78
79edma_tptc2: tptc@49a00000 {
80	compatible = "ti,edma3-tptc";
81	ti,hwmods = "tptc2";
82	reg =	<0x49a00000 0x100000>;
83	interrupts = <114>;
84	interrupt-names = "edm3_tcerrint";
85};
86
87sham: sham@53100000 {
88	compatible = "ti,omap4-sham";
89	ti,hwmods = "sham";
90	reg = <0x53100000 0x200>;
91	interrupts = <109>;
92	/* DMA channel 36 executed on eDMA TC0 - low priority queue */
93	dmas = <&edma 36 0>;
94	dma-names = "rx";
95};
96
97mcasp0: mcasp@48038000 {
98	compatible = "ti,am33xx-mcasp-audio";
99	ti,hwmods = "mcasp0";
100	reg = <0x48038000 0x2000>,
101		<0x46000000 0x400000>;
102	reg-names = "mpu", "dat";
103	interrupts = <80>, <81>;
104	interrupt-names = "tx", "rx";
105	status = "disabled";
106	/* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
107	dmas = <&edma 8 2>,
108	       <&edma 9 2>;
109	dma-names = "tx", "rx";
110};
111
112------------------------------------------------------------------------------
113DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
114binding.
115
116Required properties:
117- compatible : "ti,edma3"
118- #dma-cells: Should be set to <1>
119              Clients should use a single channel number per DMA request.
120- reg: Memory map for accessing module
121- interrupt-parent: Interrupt controller the interrupt is routed through
122- interrupts: Exactly 3 interrupts need to be specified in the order:
123              1. Transfer completion interrupt.
124              2. Memory protection interrupt.
125              3. Error interrupt.
126Optional properties:
127- ti,hwmods: Name of the hwmods associated to the EDMA
128- ti,edma-xbar-event-map: Crossbar event to channel map
129
130Deprecated properties:
131Listed here in case one wants to boot an old kernel with new DTB. These
132properties might need to be added to the new DTS files.
133- ti,edma-regions: Number of regions
134- ti,edma-slots: Number of slots
135- dma-channels: Specify total DMA channels per CC
136
137Example:
138
139edma: edma@49000000 {
140	reg = <0x49000000 0x10000>;
141	interrupt-parent = <&intc>;
142	interrupts = <12 13 14>;
143	compatible = "ti,edma3";
144	ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
145	#dma-cells = <1>;
146	ti,edma-xbar-event-map = /bits/ 16 <1 12
147					    2 13>;
148};
149