1Texas Instruments eDMA
2
3The eDMA3 consists of two components: Channel controller (CC) and Transfer
4Controller(s) (TC). The CC is the main entry for DMA users since it is
5responsible for the DMA channel handling, while the TCs are responsible to
6execute the actual DMA tansfer.
7
8------------------------------------------------------------------------------
9eDMA3 Channel Controller
10
11Required properties:
12--------------------
13- compatible:	Should be:
14		- "ti,edma3-tpcc" for the channel controller(s) on OMAP,
15		  AM33xx and AM43xx SoCs.
16		- "ti,k2g-edma3-tpcc", "ti,edma3-tpcc" for the
17		  channel controller(s) on 66AK2G.
18- #dma-cells:	Should be set to <2>. The first number is the DMA request
19		number and the second is the TC the channel is serviced on.
20- reg:		Memory map of eDMA CC
21- reg-names:	"edma3_cc"
22- interrupts:	Interrupt lines for CCINT, MPERR and CCERRINT.
23- interrupt-names: "edma3_ccint", "edma3_mperr" and "edma3_ccerrint"
24- ti,tptcs:	List of TPTCs associated with the eDMA in the following form:
25		<&tptc_phandle TC_priority_number>. The highest priority is 0.
26
27SoC-specific Required properties:
28--------------------------------
29The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
30- ti,hwmods:	Name of the hwmods associated to the eDMA CC.
31
32The following are mandatory properties for 66AK2G SoCs only:
33- power-domains:Should contain a phandle to a PM domain provider node
34		and an args specifier containing the device id
35		value. This property is as per the binding,
36		Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
37
38Optional properties:
39-------------------
40- ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow
41		these channels will be SW triggered channels. See example.
42- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by
43		the driver, they are allocated to be used by for example the
44		DSP. See example.
45
46------------------------------------------------------------------------------
47eDMA3 Transfer Controller
48
49Required properties:
50--------------------
51- compatible:	Should be:
52		- "ti,edma3-tptc" for the transfer controller(s) on OMAP,
53		  AM33xx and AM43xx SoCs.
54		- "ti,k2g-edma3-tptc", "ti,edma3-tptc" for the
55		  transfer controller(s) on 66AK2G.
56- reg:		Memory map of eDMA TC
57- interrupts:	Interrupt number for TCerrint.
58
59SoC-specific Required properties:
60--------------------------------
61The following are mandatory properties for OMAP, AM33xx and AM43xx SoCs only:
62- ti,hwmods:	Name of the hwmods associated to the eDMA TC.
63
64The following are mandatory properties for 66AK2G SoCs only:
65- power-domains:Should contain a phandle to a PM domain provider node
66		and an args specifier containing the device id
67		value. This property is as per the binding,
68		Documentation/devicetree/bindings/soc/ti/sci-pm-domain.txt
69
70Optional properties:
71-------------------
72- interrupt-names: "edma3_tcerrint"
73
74------------------------------------------------------------------------------
75Examples:
76
771.
78edma: edma@49000000 {
79	compatible = "ti,edma3-tpcc";
80	ti,hwmods = "tpcc";
81	reg =	<0x49000000 0x10000>;
82	reg-names = "edma3_cc";
83	interrupts = <12 13 14>;
84	interrupt-names = "edma3_ccint", "edma3_mperr", "edma3_ccerrint";
85	dma-requests = <64>;
86	#dma-cells = <2>;
87
88	ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>;
89
90	/* Channel 20 and 21 is allocated for memcpy */
91	ti,edma-memcpy-channels = <20 21>;
92	/* The following PaRAM slots are reserved: 35-44 and 100-109 */
93	ti,edma-reserved-slot-ranges = <35 10>, <100 10>;
94};
95
96edma_tptc0: tptc@49800000 {
97	compatible = "ti,edma3-tptc";
98	ti,hwmods = "tptc0";
99	reg =	<0x49800000 0x100000>;
100	interrupts = <112>;
101	interrupt-names = "edm3_tcerrint";
102};
103
104edma_tptc1: tptc@49900000 {
105	compatible = "ti,edma3-tptc";
106	ti,hwmods = "tptc1";
107	reg =	<0x49900000 0x100000>;
108	interrupts = <113>;
109	interrupt-names = "edm3_tcerrint";
110};
111
112edma_tptc2: tptc@49a00000 {
113	compatible = "ti,edma3-tptc";
114	ti,hwmods = "tptc2";
115	reg =	<0x49a00000 0x100000>;
116	interrupts = <114>;
117	interrupt-names = "edm3_tcerrint";
118};
119
120sham: sham@53100000 {
121	compatible = "ti,omap4-sham";
122	ti,hwmods = "sham";
123	reg = <0x53100000 0x200>;
124	interrupts = <109>;
125	/* DMA channel 36 executed on eDMA TC0 - low priority queue */
126	dmas = <&edma 36 0>;
127	dma-names = "rx";
128};
129
130mcasp0: mcasp@48038000 {
131	compatible = "ti,am33xx-mcasp-audio";
132	ti,hwmods = "mcasp0";
133	reg = <0x48038000 0x2000>,
134		<0x46000000 0x400000>;
135	reg-names = "mpu", "dat";
136	interrupts = <80>, <81>;
137	interrupt-names = "tx", "rx";
138	/* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */
139	dmas = <&edma 8 2>,
140	       <&edma 9 2>;
141	dma-names = "tx", "rx";
142};
143
1442.
145edma1: edma@2728000 {
146	compatible = "ti,k2g-edma3-tpcc", "ti,edma3-tpcc";
147	reg =	<0x02728000 0x8000>;
148	reg-names = "edma3_cc";
149	interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
150			<GIC_SPI 219 IRQ_TYPE_EDGE_RISING>,
151			<GIC_SPI 220 IRQ_TYPE_EDGE_RISING>;
152	interrupt-names = "edma3_ccint", "emda3_mperr",
153			  "edma3_ccerrint";
154	dma-requests = <64>;
155	#dma-cells = <2>;
156
157	ti,tptcs = <&edma1_tptc0 7>, <&edma1_tptc1 0>;
158
159	/*
160	 * memcpy is disabled, can be enabled with:
161	 * ti,edma-memcpy-channels = <12 13 14 15>;
162	 * for example.
163	 */
164
165	power-domains = <&k2g_pds 0x4f>;
166};
167
168edma1_tptc0: tptc@27b0000 {
169	compatible = "ti,k2g-edma3-tptc", "ti,edma3-tptc";
170	reg =	<0x027b0000 0x400>;
171	power-domains = <&k2g_pds 0x4f>;
172};
173
174edma1_tptc1: tptc@27b8000 {
175	compatible = "ti, k2g-edma3-tptc", "ti,edma3-tptc";
176	reg =	<0x027b8000 0x400>;
177	power-domains = <&k2g_pds 0x4f>;
178};
179
180mmc0: mmc@23000000 {
181	compatible = "ti,k2g-hsmmc", "ti,omap4-hsmmc";
182	reg = <0x23000000 0x400>;
183	interrupts = <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>;
184	dmas = <&edma1 24 0>, <&edma1 25 0>;
185	dma-names = "tx", "rx";
186	bus-width = <4>;
187	ti,needs-special-reset;
188	no-1-8-v;
189	max-frequency = <96000000>;
190	power-domains = <&k2g_pds 0xb>;
191	clocks = <&k2g_clks 0xb 1>, <&k2g_clks 0xb 2>;
192	clock-names = "fck", "mmchsdb_fck";
193	status = "disabled";
194};
195
196------------------------------------------------------------------------------
197DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc
198binding.
199
200Required properties:
201- compatible : "ti,edma3"
202- #dma-cells: Should be set to <1>
203              Clients should use a single channel number per DMA request.
204- reg: Memory map for accessing module
205- interrupt-parent: Interrupt controller the interrupt is routed through
206- interrupts: Exactly 3 interrupts need to be specified in the order:
207              1. Transfer completion interrupt.
208              2. Memory protection interrupt.
209              3. Error interrupt.
210Optional properties:
211- ti,hwmods: Name of the hwmods associated to the EDMA
212- ti,edma-xbar-event-map: Crossbar event to channel map
213
214Deprecated properties:
215Listed here in case one wants to boot an old kernel with new DTB. These
216properties might need to be added to the new DTS files.
217- ti,edma-regions: Number of regions
218- ti,edma-slots: Number of slots
219- dma-channels: Specify total DMA channels per CC
220
221Example:
222
223edma: edma@49000000 {
224	reg = <0x49000000 0x10000>;
225	interrupt-parent = <&intc>;
226	interrupts = <12 13 14>;
227	compatible = "ti,edma3";
228	ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
229	#dma-cells = <1>;
230	ti,edma-xbar-event-map = /bits/ 16 <1 12
231					    2 13>;
232};
233