1Texas Instruments eDMA 2 3The eDMA3 consists of two components: Channel controller (CC) and Transfer 4Controller(s) (TC). The CC is the main entry for DMA users since it is 5responsible for the DMA channel handling, while the TCs are responsible to 6execute the actual DMA tansfer. 7 8------------------------------------------------------------------------------ 9eDMA3 Channel Controller 10 11Required properties: 12- compatible: "ti,edma3-tpcc" for the channel controller(s) 13- #dma-cells: Should be set to <2>. The first number is the DMA request 14 number and the second is the TC the channel is serviced on. 15- reg: Memory map of eDMA CC 16- reg-names: "edma3_cc" 17- interrupts: Interrupt lines for CCINT, MPERR and CCERRINT. 18- interrupt-names: "edma3_ccint", "emda3_mperr" and "edma3_ccerrint" 19- ti,tptcs: List of TPTCs associated with the eDMA in the following form: 20 <&tptc_phandle TC_priority_number>. The highest priority is 0. 21 22Optional properties: 23- ti,hwmods: Name of the hwmods associated to the eDMA CC 24- ti,edma-memcpy-channels: List of channels allocated to be used for memcpy, iow 25 these channels will be SW triggered channels. The list must 26 contain 16 bits numbers, see example. 27- ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by 28 the driver, they are allocated to be used by for example the 29 DSP. See example. 30 31------------------------------------------------------------------------------ 32eDMA3 Transfer Controller 33 34Required properties: 35- compatible: "ti,edma3-tptc" for the transfer controller(s) 36- reg: Memory map of eDMA TC 37- interrupts: Interrupt number for TCerrint. 38 39Optional properties: 40- ti,hwmods: Name of the hwmods associated to the given eDMA TC 41- interrupt-names: "edma3_tcerrint" 42 43------------------------------------------------------------------------------ 44Example: 45 46edma: edma@49000000 { 47 compatible = "ti,edma3-tpcc"; 48 ti,hwmods = "tpcc"; 49 reg = <0x49000000 0x10000>; 50 reg-names = "edma3_cc"; 51 interrupts = <12 13 14>; 52 interrupt-names = "edma3_ccint", "emda3_mperr", "edma3_ccerrint"; 53 dma-requests = <64>; 54 #dma-cells = <2>; 55 56 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 7>, <&edma_tptc2 0>; 57 58 /* Channel 20 and 21 is allocated for memcpy */ 59 ti,edma-memcpy-channels = /bits/ 16 <20 21>; 60 /* The following PaRAM slots are reserved: 35-45 and 100-110 */ 61 ti,edma-reserved-slot-ranges = /bits/ 16 <35 10>, 62 /bits/ 16 <100 10>; 63}; 64 65edma_tptc0: tptc@49800000 { 66 compatible = "ti,edma3-tptc"; 67 ti,hwmods = "tptc0"; 68 reg = <0x49800000 0x100000>; 69 interrupts = <112>; 70 interrupt-names = "edm3_tcerrint"; 71}; 72 73edma_tptc1: tptc@49900000 { 74 compatible = "ti,edma3-tptc"; 75 ti,hwmods = "tptc1"; 76 reg = <0x49900000 0x100000>; 77 interrupts = <113>; 78 interrupt-names = "edm3_tcerrint"; 79}; 80 81edma_tptc2: tptc@49a00000 { 82 compatible = "ti,edma3-tptc"; 83 ti,hwmods = "tptc2"; 84 reg = <0x49a00000 0x100000>; 85 interrupts = <114>; 86 interrupt-names = "edm3_tcerrint"; 87}; 88 89sham: sham@53100000 { 90 compatible = "ti,omap4-sham"; 91 ti,hwmods = "sham"; 92 reg = <0x53100000 0x200>; 93 interrupts = <109>; 94 /* DMA channel 36 executed on eDMA TC0 - low priority queue */ 95 dmas = <&edma 36 0>; 96 dma-names = "rx"; 97}; 98 99mcasp0: mcasp@48038000 { 100 compatible = "ti,am33xx-mcasp-audio"; 101 ti,hwmods = "mcasp0"; 102 reg = <0x48038000 0x2000>, 103 <0x46000000 0x400000>; 104 reg-names = "mpu", "dat"; 105 interrupts = <80>, <81>; 106 interrupt-names = "tx", "rx"; 107 status = "disabled"; 108 /* DMA channels 8 and 9 executed on eDMA TC2 - high priority queue */ 109 dmas = <&edma 8 2>, 110 <&edma 9 2>; 111 dma-names = "tx", "rx"; 112}; 113 114------------------------------------------------------------------------------ 115DEPRECATED binding, new DTS files must use the ti,edma3-tpcc/ti,edma3-tptc 116binding. 117 118Required properties: 119- compatible : "ti,edma3" 120- #dma-cells: Should be set to <1> 121 Clients should use a single channel number per DMA request. 122- reg: Memory map for accessing module 123- interrupt-parent: Interrupt controller the interrupt is routed through 124- interrupts: Exactly 3 interrupts need to be specified in the order: 125 1. Transfer completion interrupt. 126 2. Memory protection interrupt. 127 3. Error interrupt. 128Optional properties: 129- ti,hwmods: Name of the hwmods associated to the EDMA 130- ti,edma-xbar-event-map: Crossbar event to channel map 131 132Deprecated properties: 133Listed here in case one wants to boot an old kernel with new DTB. These 134properties might need to be added to the new DTS files. 135- ti,edma-regions: Number of regions 136- ti,edma-slots: Number of slots 137- dma-channels: Specify total DMA channels per CC 138 139Example: 140 141edma: edma@49000000 { 142 reg = <0x49000000 0x10000>; 143 interrupt-parent = <&intc>; 144 interrupts = <12 13 14>; 145 compatible = "ti,edma3"; 146 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2"; 147 #dma-cells = <1>; 148 ti,edma-xbar-event-map = /bits/ 16 <1 12 149 2 13>; 150}; 151