1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/snps,dw-axi-dmac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare AXI DMA Controller
8
9maintainers:
10  - Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
11
12description:
13  Synopsys DesignWare AXI DMA Controller DT Binding
14
15allOf:
16  - $ref: dma-controller.yaml#
17
18properties:
19  compatible:
20    enum:
21      - snps,axi-dma-1.01a
22      - intel,kmb-axi-dma
23
24  reg:
25    minItems: 1
26    items:
27      - description: Address range of the DMAC registers
28      - description: Address range of the DMAC APB registers
29
30  reg-names:
31    items:
32      - const: axidma_ctrl_regs
33      - const: axidma_apb_regs
34
35  interrupts:
36    description:
37      If the IP-core synthesis parameter DMAX_INTR_IO_TYPE is set to 1, this
38      will be per-channel interrupts. Otherwise, this is a single combined IRQ
39      for all channels.
40    minItems: 1
41    maxItems: 8
42
43  clocks:
44    items:
45      - description: Bus Clock
46      - description: Module Clock
47
48  clock-names:
49    items:
50      - const: core-clk
51      - const: cfgr-clk
52
53  '#dma-cells':
54    const: 1
55
56  dma-channels:
57    minimum: 1
58    maximum: 8
59
60  resets:
61    maxItems: 1
62
63  snps,dma-masters:
64    description: |
65      Number of AXI masters supported by the hardware.
66    $ref: /schemas/types.yaml#/definitions/uint32
67    enum: [1, 2]
68
69  snps,data-width:
70    description: |
71      AXI data width supported by hardware.
72      (0 - 8bits, 1 - 16bits, 2 - 32bits, ..., 6 - 512bits)
73    $ref: /schemas/types.yaml#/definitions/uint32
74    enum: [0, 1, 2, 3, 4, 5, 6]
75
76  snps,priority:
77    description: |
78      Channel priority specifier associated with the DMA channels.
79    $ref: /schemas/types.yaml#/definitions/uint32-array
80    minItems: 1
81    maxItems: 8
82
83  snps,block-size:
84    description: |
85      Channel block size specifier associated with the DMA channels.
86    $ref: /schemas/types.yaml#/definitions/uint32-array
87    minItems: 1
88    maxItems: 8
89
90  snps,axi-max-burst-len:
91    description: |
92      Restrict master AXI burst length by value specified in this property.
93      If this property is missing the maximum AXI burst length supported by
94      DMAC is used.
95    $ref: /schemas/types.yaml#/definitions/uint32
96    minimum: 1
97    maximum: 256
98
99required:
100  - compatible
101  - reg
102  - clocks
103  - clock-names
104  - interrupts
105  - '#dma-cells'
106  - dma-channels
107  - snps,dma-masters
108  - snps,data-width
109  - snps,priority
110  - snps,block-size
111
112additionalProperties: false
113
114examples:
115  - |
116    #include <dt-bindings/interrupt-controller/arm-gic.h>
117    #include <dt-bindings/interrupt-controller/irq.h>
118    /* example with snps,dw-axi-dmac */
119    dma-controller@80000 {
120        compatible = "snps,axi-dma-1.01a";
121        reg = <0x80000 0x400>;
122        clocks = <&core_clk>, <&cfgr_clk>;
123        clock-names = "core-clk", "cfgr-clk";
124        interrupt-parent = <&intc>;
125        interrupts = <27>;
126        #dma-cells = <1>;
127        dma-channels = <4>;
128        snps,dma-masters = <2>;
129        snps,data-width = <3>;
130        snps,block-size = <4096 4096 4096 4096>;
131        snps,priority = <0 1 2 3>;
132        snps,axi-max-burst-len = <16>;
133    };
134