1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/renesas,rcar-dmac.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Renesas R-Car and RZ/G DMA Controller
8
9maintainers:
10  - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
11
12allOf:
13  - $ref: "dma-controller.yaml#"
14
15properties:
16  compatible:
17    items:
18      - enum:
19          - renesas,dmac-r8a7742  # RZ/G1H
20          - renesas,dmac-r8a7743  # RZ/G1M
21          - renesas,dmac-r8a7744  # RZ/G1N
22          - renesas,dmac-r8a7745  # RZ/G1E
23          - renesas,dmac-r8a77470 # RZ/G1C
24          - renesas,dmac-r8a774a1 # RZ/G2M
25          - renesas,dmac-r8a774b1 # RZ/G2N
26          - renesas,dmac-r8a774c0 # RZ/G2E
27          - renesas,dmac-r8a774e1 # RZ/G2H
28          - renesas,dmac-r8a7790  # R-Car H2
29          - renesas,dmac-r8a7791  # R-Car M2-W
30          - renesas,dmac-r8a7792  # R-Car V2H
31          - renesas,dmac-r8a7793  # R-Car M2-N
32          - renesas,dmac-r8a7794  # R-Car E2
33          - renesas,dmac-r8a7795  # R-Car H3
34          - renesas,dmac-r8a7796  # R-Car M3-W
35          - renesas,dmac-r8a77961 # R-Car M3-W+
36          - renesas,dmac-r8a77965 # R-Car M3-N
37          - renesas,dmac-r8a77970 # R-Car V3M
38          - renesas,dmac-r8a77980 # R-Car V3H
39          - renesas,dmac-r8a77990 # R-Car E3
40          - renesas,dmac-r8a77995 # R-Car D3
41      - const: renesas,rcar-dmac
42
43  reg:
44    maxItems: 1
45
46  interrupts:
47    minItems: 9
48    maxItems: 17
49
50  interrupt-names:
51    minItems: 9
52    maxItems: 17
53    items:
54      - const: error
55      - pattern: "^ch([0-9]|1[0-5])$"
56      - pattern: "^ch([0-9]|1[0-5])$"
57      - pattern: "^ch([0-9]|1[0-5])$"
58      - pattern: "^ch([0-9]|1[0-5])$"
59      - pattern: "^ch([0-9]|1[0-5])$"
60      - pattern: "^ch([0-9]|1[0-5])$"
61      - pattern: "^ch([0-9]|1[0-5])$"
62      - pattern: "^ch([0-9]|1[0-5])$"
63      - pattern: "^ch([0-9]|1[0-5])$"
64      - pattern: "^ch([0-9]|1[0-5])$"
65      - pattern: "^ch([0-9]|1[0-5])$"
66      - pattern: "^ch([0-9]|1[0-5])$"
67      - pattern: "^ch([0-9]|1[0-5])$"
68      - pattern: "^ch([0-9]|1[0-5])$"
69      - pattern: "^ch([0-9]|1[0-5])$"
70      - pattern: "^ch([0-9]|1[0-5])$"
71
72  clocks:
73    maxItems: 1
74
75  clock-names:
76    items:
77      - const: fck
78
79  '#dma-cells':
80    const: 1
81    description:
82      The cell specifies the MID/RID of the DMAC port connected to
83      the DMA client.
84
85  dma-channels:
86    minimum: 8
87    maximum: 16
88
89  dma-channel-mask: true
90
91  iommus:
92    minItems: 8
93    maxItems: 16
94
95  power-domains:
96    maxItems: 1
97
98  resets:
99    maxItems: 1
100
101required:
102  - compatible
103  - reg
104  - interrupts
105  - interrupt-names
106  - clocks
107  - clock-names
108  - '#dma-cells'
109  - dma-channels
110  - power-domains
111  - resets
112
113additionalProperties: false
114
115examples:
116  - |
117    #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
118    #include <dt-bindings/interrupt-controller/arm-gic.h>
119    #include <dt-bindings/power/r8a7790-sysc.h>
120
121    dmac0: dma-controller@e6700000 {
122        compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
123        reg = <0xe6700000 0x20000>;
124        interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
125                     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
126                     <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
127                     <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
128                     <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
129                     <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
130                     <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
131                     <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
132                     <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
133                     <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
134                     <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
135                     <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
136                     <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
137                     <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
138                     <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
139                     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
140        interrupt-names = "error",
141                          "ch0", "ch1", "ch2", "ch3",
142                          "ch4", "ch5", "ch6", "ch7",
143                          "ch8", "ch9", "ch10", "ch11",
144                          "ch12", "ch13", "ch14";
145        clocks = <&cpg CPG_MOD 219>;
146        clock-names = "fck";
147        power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
148        resets = <&cpg 219>;
149        #dma-cells = <1>;
150        dma-channels = <15>;
151    };
152