1*9b9b1253SBiju Das# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*9b9b1253SBiju Das%YAML 1.2 3*9b9b1253SBiju Das--- 4*9b9b1253SBiju Das$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml# 5*9b9b1253SBiju Das$schema: http://devicetree.org/meta-schemas/core.yaml# 6*9b9b1253SBiju Das 7*9b9b1253SBiju Dastitle: Renesas RZ/G2L DMA Controller 8*9b9b1253SBiju Das 9*9b9b1253SBiju Dasmaintainers: 10*9b9b1253SBiju Das - Biju Das <biju.das.jz@bp.renesas.com> 11*9b9b1253SBiju Das 12*9b9b1253SBiju DasallOf: 13*9b9b1253SBiju Das - $ref: "dma-controller.yaml#" 14*9b9b1253SBiju Das 15*9b9b1253SBiju Dasproperties: 16*9b9b1253SBiju Das compatible: 17*9b9b1253SBiju Das items: 18*9b9b1253SBiju Das - enum: 19*9b9b1253SBiju Das - renesas,r9a07g044-dmac # RZ/G2{L,LC} 20*9b9b1253SBiju Das - const: renesas,rz-dmac 21*9b9b1253SBiju Das 22*9b9b1253SBiju Das reg: 23*9b9b1253SBiju Das items: 24*9b9b1253SBiju Das - description: Control and channel register block 25*9b9b1253SBiju Das - description: DMA extended resource selector block 26*9b9b1253SBiju Das 27*9b9b1253SBiju Das interrupts: 28*9b9b1253SBiju Das maxItems: 17 29*9b9b1253SBiju Das 30*9b9b1253SBiju Das interrupt-names: 31*9b9b1253SBiju Das items: 32*9b9b1253SBiju Das - const: error 33*9b9b1253SBiju Das - const: ch0 34*9b9b1253SBiju Das - const: ch1 35*9b9b1253SBiju Das - const: ch2 36*9b9b1253SBiju Das - const: ch3 37*9b9b1253SBiju Das - const: ch4 38*9b9b1253SBiju Das - const: ch5 39*9b9b1253SBiju Das - const: ch6 40*9b9b1253SBiju Das - const: ch7 41*9b9b1253SBiju Das - const: ch8 42*9b9b1253SBiju Das - const: ch9 43*9b9b1253SBiju Das - const: ch10 44*9b9b1253SBiju Das - const: ch11 45*9b9b1253SBiju Das - const: ch12 46*9b9b1253SBiju Das - const: ch13 47*9b9b1253SBiju Das - const: ch14 48*9b9b1253SBiju Das - const: ch15 49*9b9b1253SBiju Das 50*9b9b1253SBiju Das clocks: 51*9b9b1253SBiju Das items: 52*9b9b1253SBiju Das - description: DMA main clock 53*9b9b1253SBiju Das - description: DMA register access clock 54*9b9b1253SBiju Das 55*9b9b1253SBiju Das '#dma-cells': 56*9b9b1253SBiju Das const: 1 57*9b9b1253SBiju Das description: 58*9b9b1253SBiju Das The cell specifies the encoded MID/RID values of the DMAC port 59*9b9b1253SBiju Das connected to the DMA client and the slave channel configuration 60*9b9b1253SBiju Das parameters. 61*9b9b1253SBiju Das bits[0:9] - Specifies MID/RID value 62*9b9b1253SBiju Das bit[10] - Specifies DMA request high enable (HIEN) 63*9b9b1253SBiju Das bit[11] - Specifies DMA request detection type (LVL) 64*9b9b1253SBiju Das bits[12:14] - Specifies DMAACK output mode (AM) 65*9b9b1253SBiju Das bit[15] - Specifies Transfer Mode (TM) 66*9b9b1253SBiju Das 67*9b9b1253SBiju Das dma-channels: 68*9b9b1253SBiju Das const: 16 69*9b9b1253SBiju Das 70*9b9b1253SBiju Das power-domains: 71*9b9b1253SBiju Das maxItems: 1 72*9b9b1253SBiju Das 73*9b9b1253SBiju Das resets: 74*9b9b1253SBiju Das items: 75*9b9b1253SBiju Das - description: Reset for DMA ARESETN reset terminal 76*9b9b1253SBiju Das - description: Reset for DMA RST_ASYNC reset terminal 77*9b9b1253SBiju Das 78*9b9b1253SBiju Dasrequired: 79*9b9b1253SBiju Das - compatible 80*9b9b1253SBiju Das - reg 81*9b9b1253SBiju Das - interrupts 82*9b9b1253SBiju Das - interrupt-names 83*9b9b1253SBiju Das - clocks 84*9b9b1253SBiju Das - '#dma-cells' 85*9b9b1253SBiju Das - dma-channels 86*9b9b1253SBiju Das - power-domains 87*9b9b1253SBiju Das - resets 88*9b9b1253SBiju Das 89*9b9b1253SBiju DasadditionalProperties: false 90*9b9b1253SBiju Das 91*9b9b1253SBiju Dasexamples: 92*9b9b1253SBiju Das - | 93*9b9b1253SBiju Das #include <dt-bindings/interrupt-controller/arm-gic.h> 94*9b9b1253SBiju Das #include <dt-bindings/clock/r9a07g044-cpg.h> 95*9b9b1253SBiju Das 96*9b9b1253SBiju Das dmac: dma-controller@11820000 { 97*9b9b1253SBiju Das compatible = "renesas,r9a07g044-dmac", 98*9b9b1253SBiju Das "renesas,rz-dmac"; 99*9b9b1253SBiju Das reg = <0x11820000 0x10000>, 100*9b9b1253SBiju Das <0x11830000 0x10000>; 101*9b9b1253SBiju Das interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>, 102*9b9b1253SBiju Das <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>, 103*9b9b1253SBiju Das <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>, 104*9b9b1253SBiju Das <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>, 105*9b9b1253SBiju Das <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>, 106*9b9b1253SBiju Das <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, 107*9b9b1253SBiju Das <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>, 108*9b9b1253SBiju Das <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>, 109*9b9b1253SBiju Das <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>, 110*9b9b1253SBiju Das <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>, 111*9b9b1253SBiju Das <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, 112*9b9b1253SBiju Das <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>, 113*9b9b1253SBiju Das <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>, 114*9b9b1253SBiju Das <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>, 115*9b9b1253SBiju Das <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>, 116*9b9b1253SBiju Das <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>, 117*9b9b1253SBiju Das <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; 118*9b9b1253SBiju Das interrupt-names = "error", 119*9b9b1253SBiju Das "ch0", "ch1", "ch2", "ch3", 120*9b9b1253SBiju Das "ch4", "ch5", "ch6", "ch7", 121*9b9b1253SBiju Das "ch8", "ch9", "ch10", "ch11", 122*9b9b1253SBiju Das "ch12", "ch13", "ch14", "ch15"; 123*9b9b1253SBiju Das clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>, 124*9b9b1253SBiju Das <&cpg CPG_MOD R9A07G044_DMAC_PCLK>; 125*9b9b1253SBiju Das power-domains = <&cpg>; 126*9b9b1253SBiju Das resets = <&cpg R9A07G044_DMAC_ARESETN>, 127*9b9b1253SBiju Das <&cpg R9A07G044_DMAC_RST_ASYNC>; 128*9b9b1253SBiju Das #dma-cells = <1>; 129*9b9b1253SBiju Das dma-channels = <16>; 130*9b9b1253SBiju Das }; 131