1Qualcomm Technologies HIDMA Management interface
2
3Qualcomm Technologies HIDMA is a high speed DMA device. It only supports
4memcpy and memset capabilities. It has been designed for virtualized
5environments.
6
7Each HIDMA HW instance consists of multiple DMA channels. These channels
8share the same bandwidth. The bandwidth utilization can be parititioned
9among channels based on the priority and weight assignments.
10
11There are only two priority levels and 15 weigh assignments possible.
12
13Other parameters here determine how much of the system bus this HIDMA
14instance can use like maximum read/write request and and number of bytes to
15read/write in a single burst.
16
17Main node required properties:
18- compatible: "qcom,hidma-mgmt-1.0";
19- reg: Address range for DMA device
20- dma-channels: Number of channels supported by this DMA controller.
21- max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
22  occupy the bus for in a single transaction. A memcpy requested is
23  fragmented to multiples of this amount. This parameter is used while
24  writing into destination memory. Setting this value incorrectly can
25  starve other peripherals in the system.
26- max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
27  occupy the bus for in a single transaction. A memcpy request is
28  fragmented to multiples of this amount. This parameter is used while
29  reading the source memory. Setting this value incorrectly can starve
30  other peripherals in the system.
31- max-write-transactions: This value is how many times a write burst is
32  applied back to back while writing to the destination before yielding
33  the bus.
34- max-read-transactions: This value is how many times a read burst is
35  applied back to back while reading the source before yielding the bus.
36- channel-reset-timeout-cycles: Channel reset timeout in cycles for this SOC.
37  Once a reset is applied to the HW, HW starts a timer for reset operation
38  to confirm. If reset is not completed within this time, HW reports reset
39  failure.
40
41Sub-nodes:
42
43HIDMA has one or more DMA channels that are used to move data from one
44memory location to another.
45
46When the OS is not in control of the management interface (i.e. it's a guest),
47the channel nodes appear on their own, not under a management node.
48
49Required properties:
50- compatible: must contain "qcom,hidma-1.0"
51- reg: Addresses for the transfer and event channel
52- interrupts: Should contain the event interrupt
53- desc-count: Number of asynchronous requests this channel can handle
54- iommus: required a iommu node
55
56Example:
57
58Hypervisor OS configuration:
59
60	hidma-mgmt@f9984000 = {
61		compatible = "qcom,hidma-mgmt-1.0";
62		reg = <0xf9984000 0x15000>;
63		dma-channels = <6>;
64		max-write-burst-bytes = <1024>;
65		max-read-burst-bytes = <1024>;
66		max-write-transactions = <31>;
67		max-read-transactions = <31>;
68		channel-reset-timeout-cycles = <0x500>;
69
70		hidma_24: dma-controller@0x5c050000 {
71			compatible = "qcom,hidma-1.0";
72			reg = <0 0x5c050000 0x0 0x1000>,
73			      <0 0x5c0b0000 0x0 0x1000>;
74			interrupts = <0 389 0>;
75			desc-count = <10>;
76			iommus = <&system_mmu>;
77		};
78	};
79
80Guest OS configuration:
81
82	hidma_24: dma-controller@0x5c050000 {
83		compatible = "qcom,hidma-1.0";
84		reg = <0 0x5c050000 0x0 0x1000>,
85		      <0 0x5c0b0000 0x0 0x1000>;
86		interrupts = <0 389 0>;
87		desc-count = <10>;
88		iommus = <&system_mmu>;
89	};
90