1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies Inc GPI DMA controller
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description: |
13  QCOM GPI DMA controller provides DMA capabilities for
14  peripheral buses such as I2C, UART, and SPI.
15
16allOf:
17  - $ref: "dma-controller.yaml#"
18
19properties:
20  compatible:
21    enum:
22      - qcom,sdm845-gpi-dma
23      - qcom,sm8150-gpi-dma
24      - qcom,sm8250-gpi-dma
25
26  reg:
27    maxItems: 1
28
29  interrupts:
30    description:
31      Interrupt lines for each GPI instance
32    maxItems: 13
33
34  "#dma-cells":
35    const: 3
36    description: >
37      DMA clients must use the format described in dma.txt, giving a phandle
38      to the DMA controller plus the following 3 integer cells:
39      - channel: if set to 0xffffffff, any available channel will be allocated
40        for the client. Otherwise, the exact channel specified will be used.
41      - seid: serial id of the client as defined in the SoC documentation.
42      - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h
43
44  iommus:
45    maxItems: 1
46
47  dma-channels:
48    maximum: 31
49
50  dma-channel-mask:
51    maxItems: 1
52
53required:
54  - compatible
55  - reg
56  - interrupts
57  - "#dma-cells"
58  - iommus
59  - dma-channels
60  - dma-channel-mask
61
62additionalProperties: false
63
64examples:
65  - |
66    #include <dt-bindings/interrupt-controller/arm-gic.h>
67    #include <dt-bindings/dma/qcom-gpi.h>
68    gpi_dma0: dma-controller@800000 {
69        compatible = "qcom,sdm845-gpi-dma";
70        #dma-cells = <3>;
71        reg = <0x00800000 0x60000>;
72        iommus = <&apps_smmu 0x0016 0x0>;
73        dma-channels = <13>;
74        dma-channel-mask = <0xfa>;
75        interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
76                     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
77                     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
78                     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
79                     <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
80                     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
81                     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
82                     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
83                     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
84                     <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
85                     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
86                     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
87                     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
88    };
89
90...
91