1f7d12ef5SThomas Petazzoni* Marvell XOR engines 2f7d12ef5SThomas Petazzoni 3f7d12ef5SThomas PetazzoniRequired properties: 46f166312SLior Amsalem- compatible: Should be "marvell,orion-xor" or "marvell,armada-380-xor" 5f7d12ef5SThomas Petazzoni- reg: Should contain registers location and length (two sets) 6f7d12ef5SThomas Petazzoni the first set is the low registers, the second set the high 7f7d12ef5SThomas Petazzoni registers for the XOR engine. 8f7d12ef5SThomas Petazzoni- clocks: pointer to the reference clock 9f7d12ef5SThomas Petazzoni 10f7d12ef5SThomas PetazzoniThe DT node must also contains sub-nodes for each XOR channel that the 11f7d12ef5SThomas PetazzoniXOR engine has. Those sub-nodes have the following required 12f7d12ef5SThomas Petazzoniproperties: 13f7d12ef5SThomas Petazzoni- interrupts: interrupt of the XOR channel 14f7d12ef5SThomas Petazzoni 15f7d12ef5SThomas PetazzoniAnd the following optional properties: 16f7d12ef5SThomas Petazzoni- dmacap,memcpy to indicate that the XOR channel is capable of memcpy operations 17f7d12ef5SThomas Petazzoni- dmacap,memset to indicate that the XOR channel is capable of memset operations 18f7d12ef5SThomas Petazzoni- dmacap,xor to indicate that the XOR channel is capable of xor operations 19f7d12ef5SThomas Petazzoni 20f7d12ef5SThomas PetazzoniExample: 21f7d12ef5SThomas Petazzoni 22f7d12ef5SThomas Petazzonixor@d0060900 { 23f7d12ef5SThomas Petazzoni compatible = "marvell,orion-xor"; 24f7d12ef5SThomas Petazzoni reg = <0xd0060900 0x100 25f7d12ef5SThomas Petazzoni 0xd0060b00 0x100>; 26f7d12ef5SThomas Petazzoni clocks = <&coreclk 0>; 27f7d12ef5SThomas Petazzoni status = "okay"; 28f7d12ef5SThomas Petazzoni 29f7d12ef5SThomas Petazzoni xor00 { 30f7d12ef5SThomas Petazzoni interrupts = <51>; 31f7d12ef5SThomas Petazzoni dmacap,memcpy; 32f7d12ef5SThomas Petazzoni dmacap,xor; 33f7d12ef5SThomas Petazzoni }; 34f7d12ef5SThomas Petazzoni xor01 { 35f7d12ef5SThomas Petazzoni interrupts = <52>; 36f7d12ef5SThomas Petazzoni dmacap,memcpy; 37f7d12ef5SThomas Petazzoni dmacap,xor; 38f7d12ef5SThomas Petazzoni dmacap,memset; 39f7d12ef5SThomas Petazzoni }; 40f7d12ef5SThomas Petazzoni}; 41