137586e0bSZhangfei Gao* MARVELL MMP DMA controller 237586e0bSZhangfei Gao 337586e0bSZhangfei GaoMarvell Peripheral DMA Controller 4af98715fSLaurent PinchartUsed platforms: pxa688, pxa910, pxa3xx, etc 537586e0bSZhangfei Gao 637586e0bSZhangfei GaoRequired properties: 737586e0bSZhangfei Gao- compatible: Should be "marvell,pdma-1.0" 837586e0bSZhangfei Gao- reg: Should contain DMA registers location and length. 937586e0bSZhangfei Gao- interrupts: Either contain all of the per-channel DMA interrupts 1037586e0bSZhangfei Gao or one irq for pdma device 11af98715fSLaurent Pinchart 12af98715fSLaurent PinchartOptional properties: 13af98715fSLaurent Pinchart- #dma-channels: Number of DMA channels supported by the controller (defaults 14af98715fSLaurent Pinchart to 32 when not specified) 159ab9ae55SRobert Jarzmik- #dma-requests: Number of DMA requestor lines supported by the controller 169ab9ae55SRobert Jarzmik (defaults to 32 when not specified) 1737586e0bSZhangfei Gao 1837586e0bSZhangfei Gao"marvell,pdma-1.0" 19af98715fSLaurent PinchartUsed platforms: pxa25x, pxa27x, pxa3xx, pxa93x, pxa168, pxa910, pxa688. 2037586e0bSZhangfei Gao 2137586e0bSZhangfei GaoExamples: 2237586e0bSZhangfei Gao 2337586e0bSZhangfei Gao/* 2437586e0bSZhangfei Gao * Each channel has specific irq 2537586e0bSZhangfei Gao * ICU parse out irq channel from ICU register, 2637586e0bSZhangfei Gao * while DMA controller may not able to distinguish the irq channel 2737586e0bSZhangfei Gao * Using this method, interrupt-parent is required as demuxer 2837586e0bSZhangfei Gao * For example, pxa688 icu register 0x128, bit 0~15 is PDMA channel irq, 2937586e0bSZhangfei Gao * 18~21 is ADMA irq 3037586e0bSZhangfei Gao */ 3137586e0bSZhangfei Gaopdma: dma-controller@d4000000 { 3237586e0bSZhangfei Gao compatible = "marvell,pdma-1.0"; 3337586e0bSZhangfei Gao reg = <0xd4000000 0x10000>; 3437586e0bSZhangfei Gao interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; 3537586e0bSZhangfei Gao interrupt-parent = <&intcmux32>; 3637586e0bSZhangfei Gao #dma-channels = <16>; 3737586e0bSZhangfei Gao }; 3837586e0bSZhangfei Gao 3937586e0bSZhangfei Gao/* 4037586e0bSZhangfei Gao * One irq for all channels 4137586e0bSZhangfei Gao * Dmaengine driver (DMA controller) distinguish irq channel via 4237586e0bSZhangfei Gao * parsing internal register 4337586e0bSZhangfei Gao */ 4437586e0bSZhangfei Gaopdma: dma-controller@d4000000 { 4537586e0bSZhangfei Gao compatible = "marvell,pdma-1.0"; 4637586e0bSZhangfei Gao reg = <0xd4000000 0x10000>; 4737586e0bSZhangfei Gao interrupts = <47>; 4837586e0bSZhangfei Gao #dma-channels = <16>; 4937586e0bSZhangfei Gao }; 5037586e0bSZhangfei Gao 5137586e0bSZhangfei Gao 5237586e0bSZhangfei GaoMarvell Two Channel DMA Controller used specifically for audio 53af98715fSLaurent PinchartUsed platforms: pxa688, pxa910 5437586e0bSZhangfei Gao 5537586e0bSZhangfei GaoRequired properties: 5637586e0bSZhangfei Gao- compatible: Should be "marvell,adma-1.0" or "marvell,pxa910-squ" 5737586e0bSZhangfei Gao- reg: Should contain DMA registers location and length. 5837586e0bSZhangfei Gao- interrupts: Either contain all of the per-channel DMA interrupts 5937586e0bSZhangfei Gao or one irq for dma device 6037586e0bSZhangfei Gao 6137586e0bSZhangfei Gao"marvell,adma-1.0" used on pxa688 6237586e0bSZhangfei Gao"marvell,pxa910-squ" used on pxa910 6337586e0bSZhangfei Gao 6437586e0bSZhangfei GaoExamples: 6537586e0bSZhangfei Gao 6637586e0bSZhangfei Gao/* each channel has specific irq */ 6737586e0bSZhangfei Gaoadma0: dma-controller@d42a0800 { 6837586e0bSZhangfei Gao compatible = "marvell,adma-1.0"; 6937586e0bSZhangfei Gao reg = <0xd42a0800 0x100>; 7037586e0bSZhangfei Gao interrupts = <18 19>; 7137586e0bSZhangfei Gao interrupt-parent = <&intcmux32>; 7237586e0bSZhangfei Gao }; 7337586e0bSZhangfei Gao 7437586e0bSZhangfei Gao/* One irq for all channels */ 7537586e0bSZhangfei Gaosqu: dma-controller@d42a0800 { 7637586e0bSZhangfei Gao compatible = "marvell,pxa910-squ"; 7737586e0bSZhangfei Gao reg = <0xd42a0800 0x100>; 7837586e0bSZhangfei Gao interrupts = <46>; 7937586e0bSZhangfei Gao }; 80